The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain

Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures

“…When considering the electrical performance of high-performance computing integrated circuits (ICs) [1] beneficial to artificial intelligence systems [2], 5G communication systems [3], smart devices [4], driverless systems [5], and cloud computing [6], the operating speed in the ON state [7], power consumption [8], RC delay [9], and leakage related to the standby current [10] in the OFF state are the chief factors of these advanced ICs. As semiconductor process manufacturing enters the nano-node era, strain technology with contact-etch-stop-layer process [11]; stress memorization technology [12]; source/drain (S/D) refilling [13]; high-k (HK) dielectrics [14]; gate-last process with low-resistance metal in the frontend of the line [15]; and low-k dielectrics [16] and copper process [17] in the backend of line are being developed. In addition, advanced processes are required to improve the performance and reduce the power consumption of ICs.…”