The effect of thermal treatment induced inter-diffusion at the interfaces on the charge trapping performance of HfO2/Al2O3 nanolaminate-based memory devices

Lan, Xuexin; Ou, Xiaoxia; Cao, Yan‐Qiang; Tang, Shi-Yu; Gong, Chang‐De; Xu, Bin; Xia, Yidong; Yin, Jiang; Li, Aidong; Yan, Feng; Liu, Zhiguo

doi:10.1063/1.4816463

Cited by 56 publications

(27 citation statements)

References 27 publications

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“…22,23 When V g is swept toward a high positive value, electrons can tunnel through the 3 nm-thick Al 2 O 3 barrier into HfO 2 charge trapping layer by means of Fowler-Nordheim (FN) tunneling. 24,25 The resultant accumulation of electrons in HfO 2 trapping layer screens the control-gate electric field to reach the silicon channel, which results in a positive shift of the threshold voltage. When V g is swept from the positive to the negative direction, however, electrons are transferred back from the HfO 2 charge trapping layer to the channel; simultaneously holes tunnel through the barrier and are trapped in the HfO 2 layer which causes the threshold shifting to the negative direction.…”

Section: Resultsmentioning

confidence: 99%

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Hou¹,

Zhang²,

Yin³

et al. 2017

ECS J. Solid State Sci. Technol.

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A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

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Section: Resultsmentioning

confidence: 99%

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Hou¹,

Zhang²,

Yin³

et al. 2017

ECS J. Solid State Sci. Technol.

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“…3(b), the planar density of the trapped charges at an applied gate voltage of ±13 V is estimated as 5.37 × 10 12 cm −2 , a little lower than that annealed at 200 • C. It means that the post annealing in N 2 can slightly reduce the density of the defects in Hf 0.5 Zr 0.5 O 2 films. Due to the possible inter-diffusion at the interface Al 2 O 3 /Hf 0.5 Zr 0.5 O 2 during the post-annealing process at high temperature, 20 the further annealing process at higher temperature was avoided.…”

Section: Resultsmentioning

confidence: 99%

“…A charge-trapping memory (CTM) structure was designed to measure the density of the defect states in Hf 0.5 Zr 0.5 O 2 film, 20 as schematically shown in Fig. 1, in which Al 2 O 3 films are employed as the tunneling layer and the blocking layers, and the charge-trapping layer is Hf 0.5 Zr 0.5 O 2 film.…”

Section: Methodsmentioning

confidence: 99%

Determination of the density of the defect states in Hf0.5Zr0.5O2 high-k film Deposited by using rf-magnetron sputtering technique

Lü

et al. 2014

AIP Advances

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A memory structure Pt/Al2O3/Hf0.5Zr0.5O2/Al2O3/p-Si was fabricated by using atomic layer deposition and rf-magnetron sputtering techniques, and its microstructure has been investigated by using the high resolution transmission electron microscopy (HRTEM). By measuring the applied gate voltage dependence of the capacitance for the memory structure, the planar density of the trapped charges in Hf0.5Zr0.5O2 high-k film was estimated as 6.63 × 1012 cm−2, indicating a body defect density of larger than 2.21 × 1019 cm−3. It is observed that the post-annealing in N2 can reduces the defect density in Hf0.5Zr0.5O2 film, which was ascribed to the occupancy of oxygen vacancies by nitrogen atoms.

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“…21 It was also reported that the multilayered high-k charge-trapping layer, such as HfO 2 /Al 2 O 3 /HfO 2 and ZrO 2 /Al 2 O 3 /ZrO 2 etc., causes an enhancement of the charge-storage efficiency of the CTM devices. [22][23][24][25][26] In our previous study, a remarkable charge-trapping efficiency and a fast programming/erasing(P/E) speed were obtained in a CTM device with a TiAlO high-k composite chargetrapping dielectric, achieving a density of trapped charges of 9.3×10 20 …”

Section: -14mentioning

confidence: 99%

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

Lü

Gong

et al. 2014

AIP Advances

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The memory structures Pt/Al2O3/(TiO2)x(Al2O3)1−x/Al2O3/p-Si(nominal composition x = 0.05, 0.50 and 0.70) were fabricated by using rf-magnetron sputtering and atomic layer deposition techniques, in which the dielectric constant and the bottom of the conduction band of the high-k composite (TiO2)x(Al2O3)1−x were adjusted by controlling the partial composition of Al2O3. With the largest dielectric constant and the lowest deviation from the bottom of the conduction band of Si, (TiO2)0.7(Al2O3)0.3 memory devices show the largest memory window of 7.54 V, the fast programming/erasing speed and excellent endurance and retention characteristics, which were ascribed to the special structural design, proper combination of dielectric constant and band alignment in the high-k composite (TiO2)0.7(Al2O3)0.3.

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The effect of thermal treatment induced inter-diffusion at the interfaces on the charge trapping performance of HfO2/Al2O3 nanolaminate-based memory devices

Cited by 56 publications

References 27 publications

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Determination of the density of the defect states in Hf0.5Zr0.5O2 high-k film Deposited by using rf-magnetron sputtering technique

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

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