The Effect of the Crystal Grown‐in Defects on the Pause Tail Characteristics of Megabit Dynamic Random Access Memory Devices

Abstract

The effect of the crystal grown-in defects on the pause tail characteristics of megabit dynamic random access memory devices was investigated. By comparing the performance of the devices fabricated on epitaxial silicon wafers with those fabricated on polished Czochralski silicon wafers, it was found that the refresh time of the memory devices fabricated on a polished silicon wafer is strongly affected by the crystal grown-in defects. Based upon the present results, the refresh time failure of the memory devices could be attributed to several types of crystal defects which include the D-defects produced as a result of vacancy aggregation during crystal growth and those associated with oxygen precipitation.

Effect of Initial High Temperature Annealing and Gettering Processes on the Refresh Time of High Density Dynamic Random Access Memory Devices

“…The long refresh time of the devices fabricated on the epitaxial wafer is attributed to the fact that epitaxial silicon contains no crystal originated defects. 13 From the figure, it is clearly seen that the refresh time of a memory device has improved considerably when an initial annealing was performed at 1300~…”

“…This phenomenon, commonly observed in memory devices with a trench-type structure, is caused by crystal originated defects, as described elsewhere. 13 Comparing the result for the case of annealing in mixed 02 and N2 ambient to that in a pure H2 ambient, it may be seen that the refresh time of the devices fabricated near the edge of the wafers annealed in a pure H2 ambient improves considerably. Since the wafers originated from the same location on the crystal, it is suggested that annealing in a hydrogen gas ambient improves the refresh time of the memory devices.…”

Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design"

“…Viviani [13] combined a silicon-on-insulator structure with silicon substrates resistivities from 20 to 300 cm. One important factor that is often overlooked is that a low-resistivity substrate with a thin epi-layer is preferred to reduce latch-up and enhance yield [14], [15]. Frei [16] recently demonstrated a modified substrate structure that simultaneously achieves high latch-up immunity and high -factor inductors.…”

High Sensitivity Determination of Oxygen Distribution in Thin Epitaxial Silicon Films by Carbon Implantation‐Photoluminescence Measurement

“…To maintain production yield of large-scale integrated circuits (LSIs) with increasingly smaller elements it is very important to increase gate oxide integrity (GOI) for metal oxide semiconductor (MOS) devices and to decrease leakage current for storage capacitors. The use of a silicon epitaxial wafer (epi wafer) for LSIs has become increasingly advantageous for avoiding failures of MOS devices 1 and capacitors 2 due to grown-in defects in the Czochralski (CZ) grown silicon crystals. 3 On the other hand, low temperature processing, including low temperature epitaxy, is unavoidable to ensure the performance of the p-n junction for shrunk devices.…”