The design of the microarchitecture of UltraSPARC-I

Tremblay, M.; Greenley, D.; Normoyle, K.

doi:10.1109/5.476081

Cited by 27 publications

(9 citation statements)

References 14 publications

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“…as Alpha 21264 [9,58], MIPS 10000 [118,120], Power4 [23], PowerPC 620 [24], HP 8000 [63,64], Sun UltraSparc [109], Pentium III [22] and Athlon [97], as well as IA-64 (EPIC) processors [43]. Since performance is the main factor that drives this high-end processor market, low power techniques used in embedded microprocessors are not an option for the high-end processors.…”

Section: Challengesmentioning

confidence: 99%

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Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

112

121

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Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

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Section: Challengesmentioning

confidence: 99%

“…However, since in real machines IP C increases less than linearly with an increase in the issue width (α < 1), the condition γ ≤ 1 may not be sufficient for a design to be energy efficient. If fact, for an Amdahl's law-like α of 0.5 [109] we have:…”

Section: Energy Models Of Functional Unitsmentioning

confidence: 99%

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

112

121

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“…This approach was first used for graphics instructions [9], [10]. Then RISC processors for workstations [11], [12] to process MPEG decoding followed. Recent microprocessors for PC's [13] also employ this approach.…”

Section: A Historymentioning

confidence: 99%

“…6. These instructions are implemented in either an integer data path [22], [23] or a floating-point (or a coprocessor) data path [12], [13] in microprocessors.…”

Section: A General-purpose Microprocessors (Risc and Cisc)mentioning

confidence: 99%

Multimedia processors

Kuroda

Nishitani

1998

Proc. IEEE

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This paper describes recent large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. Recent general-purpose microprocessors for workstations and personal computers (PC's) use special built-in hardware for multimedia processing, so the multimedia processors described in this paper include these modified general-purpose microprocessors. After briefly reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PC's, embedded RISC's, low-power digital signal processors (DSP's), which are mainly used for mobile communications devices, and media processors that support PC's for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSP's. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including "system on a chip," and their applications are also discussed.

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“…In spite of the performance of the recent RISC processors such as DEC21164, UltraSparc-I and PowerPC [18][19][20], a single processor system cannot perform the medium and high-level image processing in real-time. On the other hand, the medium-and high-level image processing is potentially parallel.…”

Section: Medium-and High-level Image Processing Processing Elementmentioning

confidence: 99%