The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Hoe, David H. K.; Jin, Xiaoyu

doi:10.1155/2015/312639

Cited by 9 publications

(5 citation statements)

References 46 publications

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“…Figure 9 show a boxplot representation of the obtained results for each algorithm. [15] 180 nm 0.799 [24] 180 nm 0.8229…”

Section: Resultsmentioning

confidence: 99%

“…The objective function and design constraints of LNA circuit are highlighted in this section. The main objective is the minimization of noise factor F, which it obtained at resonance and has an expression as follows [24,22]:…”

Section: Objective Functionmentioning

confidence: 99%

“…Where, Pmax is the maximum power dissipation. For gm and gd0 their expressions are given as follows [24]…”

Section: Constraintsmentioning

confidence: 99%

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Low Noise Amplifier Design via Hybrid DE-ACO Optimization Algorithm

Abi¹

2020

IJATCSE

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This paper presents a hybrid algorithm named (DE-ACO) which is combining two well-known nature-inspired algorithms namely Ant Colony Optimization (ACO) and Differential Evolution (DE). The main idea of this hybridization is to improve the performance of the ACO algorithm, it consists to use the DE algorithm to explore the promising search space in order to exploit the best solutions by the ACO algorithm to achieve the optimal solution. The performance of the proposed technique is firstly, evaluated over some test functions, and secondly, employed to optimize the parameters of Low Noise Amplifier (LNA) circuit. The simulation using Advanced Design System (ADS) are given to highlight the validity of this proposed method.

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“…Figure 9 show a boxplot representation of the obtained results for each algorithm. [15] 180 nm 0.799 [24] 180 nm 0.8229…”

Section: Resultsmentioning

confidence: 99%

Section: Objective Functionmentioning

confidence: 99%

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Low Noise Amplifier Design via Hybrid DE-ACO Optimization Algorithm

Abi¹

2020

IJATCSE

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“…Furthermore, the noise from the MOSFET's source and bulk resistance is considered minimal and not taken into account for this analysis, as stated in references [33], [34]. The analysis focuses on the four primary noise sources that affect the output, namely 𝑖̅ 𝑜,𝑅𝑠 , 𝑖̅ 𝑜,𝑑 , 𝑖̅ 𝑜,𝑔 , 𝑖̅ 𝑜,𝑅𝑜𝑢𝑡 respectively [35]. The noise sources expressions are summarized in Table 3…”

Section: Application Example: Low Noise Amplifier Design 41 Low Noise...mentioning

confidence: 99%

Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

2023

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This paper presents the application of two swarm intelligence techniques, multi-objective artificial bee colony (MOABC) and multi-objective particle swarm optimization (MOPSO), to the optimal design of a complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) cascode with inductive source degeneration. The aim is to achieve a balanced trade-off between voltage gain and noise figure. The optimized LNA circuit operates at 2.4 GHz with a 1.8 V power supply and is implemented in a 180 nm CMOS process. Both optimization algorithms were implemented in MATLAB and evaluated using the ZDT1, ZDT2, and ZDT3 test functions. The optimized designs were then simulated using the advance design system (ADS) simulator. The results showed that the MOABC and MOPSO techniques are practical and effective in optimizing LNA design, resulting in better performance than previously published works, with a gain of 21.2 dB and a noise figure of 0.848 dB.

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“…where W and L are the width and length of the particular transistor and V DS is the drain to source voltage of that device. Moreover, [37]. Drain current of the CG stage is reused by CS stage.…”

Section: Power Reductionmentioning

confidence: 99%

Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications

Roobert¹,

Rani²,

Rajaram³

2019

IET Circuits, Devices & Systems

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This study deals with the design and optimisation of two-stage complementary metal oxide semiconductor low noise amplifier (LNA) for wireless local area network (WLAN) applications. IEEE 802.11n WLAN standard provides up to 600 Mbps speed with 40 MHz channel bandwidth and high throughput. The receiver of these WLAN applications requires LNA with higher gain and minimum noise figure (NF). Elephant Herding Optimisation technique was involved for the first time to optimise the performance of the LNA. The post-layout simulation shows that a maximum gain of 26.7 dB at 2.4 GHz is achieved in the proposed design. Feedforward noise cancelation technique is involved to get a reduced NF of 1.12 dB. The first and second stages are tuned to cover the 3 dB maximum gain bandwidth of 3.2 GHz (from 1.7 to 4.4 GHz). This LNA is designed at 90 nm technology with the supply voltage of 0.5 and 1.2 V, and consumes 8.9 mW of power. Current reuse technology is used to reduce power consumption. The input and output return losses have been found to be −18 and −15 dB, respectively at the targeted 2.4 GHz frequency. Third-order input intercept point of the optimised LNA is −8.1 dBm.

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The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

Cited by 9 publications

References 46 publications

Low Noise Amplifier Design via Hybrid DE-ACO Optimization Algorithm

Low Noise Amplifier Design via Hybrid DE-ACO Optimization Algorithm

Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications

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