The design of high holding voltage SCR for whole-chip ESD protection

Koo, Yong-Seo; Lee, Kwang-Yeob; Kim, Kui-Dong; Kwon, Jong-Ki

doi:10.1587/elex.5.624

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…Additionally, the measurement results of the LDO regulator were measured using an oscilloscope, a DC power source, and a DC electronic load. The proposed LDO regulator can provide ESD immunity against ESD events by placing I/O clamp and power clamp on the VOUT-VSS and VDD-VSS lines, respectively [22]. In this paper, the ESD protection circuit-embedded case and the diode-embedded case were divided into measurements.…”

Section: Measurement Resultsmentioning

confidence: 99%

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

et al. 2023

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In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

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Section: Measurement Resultsmentioning

confidence: 99%

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

et al. 2023

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“…The LVTSCR ESD protection structure has improved electrical properties to effectively prevent ESD surge at a low voltage. The proposed LDO regulator has built in an LVTSCR-based ESD protection circuit to secure the high reliability of the IC circuit [18][19][20][21][22][23][24]. The proposed LDO regulator using the current driving buffer structure was secured reliably by applying ESD surge to POWER CLAMP and I/O CLAMP, and then the output voltage was verified.…”

Section: Introductionmentioning

confidence: 99%

Design of Capacitor-Less High Reliability LDO Regulator with LVTSCR Based ESD Protection Circuit Using Current Driving Buffer Structure

Kwon

Koo

2022

Electronics

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The peak voltage depending on the load current can be affected by the external capacitors installed in the output stage of the LDO regulator. However, the capacitor-less LDO regulator proposed in this study was applied a current driving buffer structure between the output stage of the error amplifier and the path transistor. Therefore, the proposed LDO regulator maintained a stable output voltage regardless of the load current by controlling an effective overshoot/undershoot voltage. In addition, the proposed LDO regulator has a built-in LVTSCR based on the ESD protection circuit. As most IC circuits are malfunctioned and destroyed by the ESD phenomenon, the reliability was verified through the built-in ESD protection circuit of the proposed LDO regulator. The proposed LDO regulator with the current driving buffer structure can effectively control the peak voltage. As a result of the measurement, the undershoot voltage of 22 mV and the overshoot voltage of 19 mV were maintained when the load current of 250 mA was provided under the conditions of 3.3 V to 4.5 V and the output power voltage of 3 V. The proposed ESD protection circuit is also guaranteed to function at temperatures as high as 500 K.

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A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps

Jae-Pil¹,

Koo²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) 0.18µm. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately 1.6Ω. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

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The design of high holding voltage SCR for whole-chip ESD protection

Cited by 3 publications

References 3 publications

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

Design of Capacitor-Less High Reliability LDO Regulator with LVTSCR Based ESD Protection Circuit Using Current Driving Buffer Structure

A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps

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