The case for the reduced instruction set computer

Patterson, David A.; Ditzel, David R.

doi:10.1145/641914.641917

Cited by 171 publications

(42 citation statements)

References 4 publications

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“…It needs to be rethought to be effective for real-time embedded systems. Patterson and Ditzel's similar observation [25] started the RISC revolution. In the same way, we must rethink real-time embedded processor architectures.…”

Section: The Pret Philosophymentioning

confidence: 79%

Predictable programming on a precision timed architecture

Lickly

Liu

Kim

et al. 2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

119

122

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In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees.We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

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Section: The Pret Philosophymentioning

confidence: 79%

Predictable programming on a precision timed architecture

Lickly

Liu

Kim

et al. 2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

119

122

View full text Add to dashboard Cite

show abstract

“…In most work on computer architecture (see e.g. [1,[19][20][21][22]), instruction sequences are under discussion. However, the notion of instruction sequence is not subjected to systematic and precise analysis in the work concerned.…”

Section: Discussionmentioning

confidence: 99%

On the Expressiveness of Single-Pass Instruction Sequences

Bergstra

Middelburg

2010

Theory Comput Syst

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We perceive programs as single-pass instruction sequences. A single-pass instruction sequence under execution is considered to produce a behaviour to be controlled by some execution environment. Threads as considered in basic thread algebra model such behaviours. We show that all regular threads, i.e. threads that can only be in a finite number of states, can be produced by single-pass instruction sequences without jump instructions if use can be made of Boolean registers. We also show that, in the case where goto instructions are used instead of jump instructions, a bound to the number of labels restricts the expressiveness.

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“…Loads to 7 of the 8 address registers had interesting side effects. A load into register A [1,2,3,4,5] resulted in the data at that address being automatically loaded into data register X [1,2,3,4,5], respectively. Similarly, loading an address into A6 or A7 resulted in a store from X6 or X7 to that address.…”

Section: Register File Designmentioning

confidence: 99%

Smart Register Files for High-Performance Microprocessors

Postiff

Mudge²

1999

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This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the most important compiler optimizations for high-speed computers because registers are the fastest storage devices in the computer system. However, register allocation has been limited in scope because of aliasing in the memory system. To break this limitation and allow more data to be placed into registers, new compiler and microarchitecture support is needed.We propose the modification of register access semantics to include an indirect access mode. We call this optimization the Smart Register File. The smart register file allows the relaxation of overly-conservative assumptions in the compiler by having the hardware provide support for aliased data items in processor registers. As a result, the compiler can allocate data from a larger pool of candidates than in a conventional system. An attendant advantage is that the smart register file reduces the number of load and store operations executed by the processor. The simple addition of an indirect register access mode not only simplifies alias handling, but also provides opportunities for other optimizations. This dissertation examines several such optimizations. Report Documentation PageForm Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

show abstract

The case for the reduced instruction set computer

Cited by 171 publications

References 4 publications

Predictable programming on a precision timed architecture

Predictable programming on a precision timed architecture

On the Expressiveness of Single-Pass Instruction Sequences

Smart Register Files for High-Performance Microprocessors

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