Smart Register Files for High-Performance Microprocessors

Abstract

This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the most important compiler optimizations for high-speed computers because registers are the fastest storage devices in the computer system. However, register allocation has been limited in scope because of aliasing in the memory system. To break this limitation and allow more data to be placed into registers, new compiler and microarchitecture support is needed.We propose the modification of register access semantics to include an indirect access mode. We call this optimization the Smart Register File. The smart register file allows the relaxation of overly-conservative assumptions in the compiler by having the hardware provide support for aliased data items in processor registers. As a result, the compiler can allocate data from a larger pool of candidates than in a conventional system. An attendant advantage is that the smart register file reduces the number of load and store operations executed by the processor. The simple addition of an indirect register access mode not only simplifies alias handling, but also provides opportunities for other optimizations. This dissertation examines several such optimizations. Report Documentation PageForm Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

Code generation for an application-specific VLIW processor with clustered, addressable register files

“…inter register file communication is partial or not supported at all. Similar to other register pointer architectures proposed in [20,23], Mephisto implements Pointer and Data registers as well but in a more segregated fashion.…”

Catch

“…Therefore, this approach offers both extra space on main memory and cache, and higher transfer rates from main memory to cache. Postiff and Mudge [1999] proposed smart-register-files aiming to solve the aliasing problem of more than one registers referring to the same datum, either address or data. Hines et al [2005] proposed the use of an instruction register file to hold frequently executed instructions.…”