Predictable programming on a precision timed architecture

Abstract

In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees.We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

A time-predictable stack cache

“…The precision timed (PRET) architecture is first presented in [8]. PRET implements a RISC pipeline and performs chiplevel multithreading for several threads to eliminate data forwarding and branch prediction [11].…”

A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems

“…This way, they can pay off the related cost more easily. Instead, modifying current general-purpose architectures, as in [34], is an appealing approach. However, in this particular example, the modifications were significant.…”

Investigation of Scratchpad Memory for Preemptive Multitasking

“…MSRS may be regarded as an improvement of earlier approaches to prevent one task evicting local memory resources used by another, such as static cache locking [29] and static SPM partitioning [9], [7]. Simpler forms of MSRS have been proposed [30], [9], but the one used in this paper has the important distinction of enabling any task to use an arbitrary number of blocks in SPM independently of all other tasks [10].…”

“…There has been recent interest in using SPM within realtime systems instead of cache [5], [6], [7], [8]. But support for preemptive multitasking is a problem: how should the SPM be managed if tasks can preempt each other?…”