The associative-skew clock routing problem

Abstract

We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative skew problem is easier to address within current EDA frameworks than useful-skew (skew-scheduling) approaches, and defines an interesting tradeoff between the traditional zero-skew clock routing problem (one sink group) and the Steiner minimum tree problem (n sink groups). We present a set of heuristic building blocks, including an efficient and optimal method of merging two zero-skew trees such that zero skew is preserved within the sink sets of each tree. Finally, we list a number of open issues for research and practical application.

Associative Skew Clock Routing for Difficult Instances

“…In an associative skew clock routing problem [3], the clock sinks are partitioned into a few groups. Skew constraints are required only within each group and do not exist between different groups.…”

“…To the best of our knowledge, [3] is the only previous work attempting to solve this problem. Although several heuristic solutions were proposed in [3], all of them are based on a very primitive delay model which equalizes clock signal delay with geometrical path length.…”

“…Although several heuristic solutions were proposed in [3], all of them are based on a very primitive delay model which equalizes clock signal delay with geometrical path length. Moreover, they are effective only when the sink groups are geometrically separated from each other.…”

A practical clock tree synthesis for semi-synchronous circuits

“…Inoue et al [12] showed that a smaller clock tree is obtained by setting the clock-input timings between the neighboring registers as small as possible. Chen et al [13] proposed the associated skew problem in which registers of the same clock timings are clustered. They claimed their approaches provide smaller VTCT, though they did not examine the actual circuits [11][12][13].…”

“…Chen et al [13] proposed the associated skew problem in which registers of the same clock timings are clustered. They claimed their approaches provide smaller VTCT, though they did not examine the actual circuits [11][12][13]. Furthermore, there still remains the second difficulty in these approaches.…”