Associative Skew Clock Routing for Difficult Instances

In the physical design of integrated circuits, the traditional clock tree synthesis is difficult to meet the timing convergence requirements at high frequency. This paper takes a data processing chip design based on TSMC 65nm 1P8M process as an example, proposes a clock tree synthesis method combining bottom-up timing convergence and useful clock skew, efficient to solving the setup time violations of chip at high frequency applications, and meeting the setting time of 0.5ns, holding time 0.15ns, effectively guarantee the timing convergence of the chip.

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Associative Skew Clock Routing for Difficult Instances

Abstract: Abstract

Cited by 2 publications

References 21 publications

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

An Efficient Timing Optimization Method in ASIC Design

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