An Efficient Timing Optimization Method in ASIC Design

Abstract

In the physical design of integrated circuits, the traditional clock tree synthesis is difficult to meet the timing convergence requirements at high frequency. This paper takes a data processing chip design based on TSMC 65nm 1P8M process as an example, proposes a clock tree synthesis method combining bottom-up timing convergence and useful clock skew, efficient to solving the setup time violations of chip at high frequency applications, and meeting the setting time of 0.5ns, holding time 0.15ns, effectively guarantee the timing convergence of the chip.