A practical clock tree synthesis for semi-synchronous circuits

Abstract

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clockinput timing of each register is a multiple of a predefined unit delay and the length of interconnection from a parent node to its child is upper bounded. The clock trees are constructed for several practical circuits. The size of each clock tree is comparable to a zero skew clock tree. In order to assure the practical quality, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3 % against the zero skew clock trees.

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

“…Fabricating circuits considering only nominal values can lead to a large percentage of dies failing to meet timing specifications. One method for considering variation is to explicitly consider a finite number of design corners [33]. However, the number of corners grows exponentially with the number of variables making it challenging to choose a proper set of corners.…”

Multi-domain clock skew scheduling

“…Toyonaga, et al [11] proposed an algorithm based on simulated annealing to synthesize a semi-synchronous clock tree optimizing a function of clock period and area. However, the focus there was on generating a feasible clock tree as opposed to finding an optimal solution for the cycle time in the clock skew scheduling problem.…”

2-SAT based linear time optimum two-domain clock skew scheduling

“…An algorithm based on simulated annealing was proposed in [5,6]. In [4], the authors formulated MDCSS problem as a mixed integer programming problem and solved it by a SATbased algorithm.…”