Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Rakai, Logan; Farshidi, Amin; Behjat, Laleh; Westwick, David T.

doi:10.1145/2451916.2451956

Cited by 14 publications

(2 citation statements)

References 39 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…T. H. Chao et al [22] proposed the Deferred Merge Embedding (DME) algorithm which is widely used in zero-skew clock routing with minimum wirelength [25] [26] [27]. As a non-ignorable part of the load capacitance, power reduction on buffers is also attached great importance by recent researches [2] [10] [17] [20]. Buffers are inserted along the paths in the clock tree at a minimum cost of power dissipation, while satisfying the constraints of skew and slew at the same time.…”

Section: Previous Workmentioning

confidence: 99%

Fast synthesis of low power clock trees based on register clustering

Deng

Cai

Zhou

2015

Sixteenth International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

Clock networks dissipate a significant fraction of the entire chip power budget. In contrast to most of the traditional works that handle the power optimization problem with clock routing or buffer sizing, we propose a novel register clustering methodology for power reduction of clock trees. Moreover, a fast three-stage clock tree synthesis (CTS) approach based on register clustering is presented to verify the validity of the methodology. By comparison with the state-of-the-art low power CTS research works Contango2.0 [21] and the CTS of Purdue University [16], our three-stage CTS approach achieves 1.30×, 1.07× smaller power consumption while exhibiting 2.01×, 1.52× smaller skew. Furthermore, the runtime of our CTS approach is 17.36×, 8.16× shorter than that of [21] and [16] respectively.

show abstract

Section: Previous Workmentioning

confidence: 99%

Fast synthesis of low power clock trees based on register clustering

Deng

Cai

Zhou

2015

Sixteenth International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…A new method of register placement calculation was proposed in [10,11] to cluster the registers in a few groups after the first placement round to decrease the clusters proportionally in order to reduce the wirelength and potential skew. Taking into account only the clock network and moving the registers without taking into account the full timing picture leads to power and timing degradation in data nets which may be more than the gain achieved in the clock tree [12].…”

Section: Introductionmentioning

confidence: 99%

A Novel Net Weighting Algorithm for Power and Timing-Driven Placement

Chentouf

Ismaili

2018

VLSI Design

View full text Add to dashboard Cite

Nowadays, many new low power ASICs applications have emerged. This new market trend made the designer’s task of meeting the timing and routability requirements within the power budget more challenging. One of the major sources of power consumption in modern integrated circuits (ICs) is the Interconnect. In this paper, we present a novel Power and Timing-Driven global Placement (PTDP) algorithm. Its principle is to wrap a commercial timing-driven placer with a nets weighting mechanism to calculate the nets weights based on their timing and power consumption. The new calculated weight is used to drive the placement engine to place the cells connected by the critical power or timing nets close to each other and hence reduce the parasitic capacitances of the interconnects and, by consequence, improve the timing and power consumption of the design. This approach not only improves the design power consumption but facilitates also the routability with only a minor impact on the timing closure of a few designs. The experiments carried on 40 industrial designs of different nodes, sizes, and complexities and demonstrate that the proposed algorithm is able to achieve significant improvements on Quality of Results (QoR) compared with a commercial timing driven placement flow. We effectively reduce the interconnect power by an average of 11.5% that leads to a total power improvement of 5.4%, a timing improvement of 9.4%, 13.7%, and of 3.2% in Worst Negative Slack (WNS), Total Negative Slack (TNS), and total wirelength reduction, respectively.

show abstract