The&amp;lt;tex&amp;gt;T_f&amp;lt;/tex&amp;gt;-equivalence class approach to analog fault diagnosis problems

Togawa, Y.; Matsumoto, Takashi; Arai, Hiroyoshi

doi:10.1109/tcs.1986.1085857

Cited by 18 publications

(3 citation statements)

References 10 publications

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“…In general, the computation is nonlinear even if the circuit is linear, although ref. 10 gives a linear branch computation algorithm for a linear circuit.…”

Section: Review Of Existing Methodsmentioning

confidence: 99%

Application of fault modeling to continuous built‐in test (c‐BIT) for microwave and MMIC circuits

Rhodes¹,

Cummings²,

Tempel³

1994

Int. J. Microw. Mill.‐Wave Comput.‐Aided Eng.

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A simulation-before-test method has been applied to the linear and nonlinear microwave built-in test (BIT) problem. Fault simulation via a harmonic balance simulator is used to analyze and optimize BIT hardware placement based on figures of merit such as fault coverage, ambiguity size, and part isolation. Fault models for a prototype microwave minisystem were developed along with models for the BIT hardware itself. The search method developed to automate the placement of BIT hardware is an essential design-for-test tool. The techniques developed were applied to an example system and results are given. 0 1994

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“…In general, the computation is nonlinear even if the circuit is linear, although ref. 10 gives a linear branch computation algorithm for a linear circuit.…”

Section: Review Of Existing Methodsmentioning

confidence: 99%

Application of fault modeling to continuous built‐in test (c‐BIT) for microwave and MMIC circuits

Rhodes¹,

Cummings²,

Tempel³

1994

Int. J. Microw. Mill.‐Wave Comput.‐Aided Eng.

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show abstract

“…Furthermore, (3) implies that one can classify faults into distinguishable classes according to their corresponding columns in , i.e., two branches and belong to the same class if rank , since both will be identified as the possible fault sites if either of them is faulty. It is shown in [13] that such classification, called the -equivalence class decomposition, is the finest possible one for fault diagnosis. The space associated with a branch is (4) Thus two branches and are in the same equivalence class, i.e., their space coincides, and therefore are not differentiable if rank (5) In such a case, given , there is no method that can tell whether is caused by or .…”

Section: B Analog Fault Diagnosismentioning

confidence: 99%

Test point selection for analog fault diagnosis of unpowered circuit boards

Huang

Cheng

2000

IEEE Trans. Circuits Syst. II

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Modern densely loaded circuit boards have posed problems for fault diagnosis with in-circuit testers because only limited physical access to the boards is allowed. In this paper, we present an efficient graph-based test-point selection algorithm for analog fault diagnosis of unpowered circuit boards. In addition to finding the sets of test points that allow one to differentiate between the elements under diagnosis, the algorithm can serve as a design for testability (DfT) guide for circuit board design. Experimental results on some industrial designs show that, in general, access to 50% of the nodes is sufficient to diagnose all the elements.Index Terms-Analog fault diagnosis, board testing, design for testability, test point selection.

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“…Numerous works [2][3][4] have been devoted to testing for catastrophic failures in analog circuits, i.e. failures that manifest themselves in a totally malfunctioned circuit.…”

Section: Fault Modelmentioning

confidence: 99%