The ACROSS MPSoC – A new generation of multi-core processors designed for safety–critical embedded systems

Salloum, C. El; Elshuber, Martin; Höftberger, Oliver; Isakovic, Haris; Wasicek, Armin

doi:10.1016/j.micpro.2013.08.002

Cited by 24 publications

(19 citation statements)

References 8 publications

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“…Two basic conditions for the mixed-criticality integration are spatial and temporal isolation [18]. These emerging properties depend on a series of interlocked architectural properties.…”

Section: Mixed-criticality Integrationmentioning

confidence: 99%

“…The architecture is built around a communication backbone called timetriggered network-on-a-chip (TTNoC) introduced in [18]. It is message based communication medium interfaced with a arbitrary number of computational components using a trusted interface subsystem (TISS)(see Figure 5).…”

Section: A Heterogeneous Time-triggered Architecture On a Hybridmentioning

confidence: 99%

“…TTNoC provides distribution of chip global time ensuring timeliness of all components. The original architecture presented in [18] implements a homogeneous set of components implemented fully in an FPGA fabric. The architecture described in [6] and presented in this paper uses underlying hybrid SoC platform to implement a heterogeneous solution that combines hard-coded processor with FPGA based set of components, interconnected with the TTNoC.…”

Section: A Heterogeneous Time-triggered Architecture On a Hybridmentioning

confidence: 99%

See 2 more Smart Citations

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Isakovic

Grosu

Ratasich

et al. 2017

Lecture Notes in Computer Science

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In the sandbox world of cyber-physical systems and internetof-things a number of applications is only eclipsed by a number of products that provide solutions for specific problem or set of problems. Initiatives like the European project EM C 2 serve as cross-disciplinary incubators for novel technologies and fuse them together with state-ofthe-art industrial applications. This paper reflects on challenges in scope of hardware architectures and related technologies. It also provides a short overview of several technologies explored in the project that provide bridging solutions for these problems.

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“…Two basic conditions for the mixed-criticality integration are spatial and temporal isolation [18]. These emerging properties depend on a series of interlocked architectural properties.…”

Section: Mixed-criticality Integrationmentioning

confidence: 99%

Section: A Heterogeneous Time-triggered Architecture On a Hybridmentioning

confidence: 99%

Section: A Heterogeneous Time-triggered Architecture On a Hybridmentioning

confidence: 99%

See 1 more Smart Citation

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Isakovic

Grosu

Ratasich

et al. 2017

Lecture Notes in Computer Science

Self Cite

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“…There is implementation technology available that readily supports the FSDM. Examples are: TTEthernet [35], TTP/C, or the ACROSS Multi-Processor System-on-Chip [37].…”

Section: Implementation Considerationsmentioning

confidence: 99%

Interfaces in Evolving Cyber-Physical Systems-of-Systems

Frömel

Kopetz

2016

Cyber-Physical Systems of Systems

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“…Mixed-criticality real-time systems support functions with different criticality on one shared system. Their importance is based on the relentless demand for increased dependability, security, more intelligence, connectivity, better performance, energy efficiency and cost-size-volume reduction in industrial systems [1] [2]. The most important advantages provided by mixed criticality are:…”

Section: Introductionmentioning

confidence: 99%

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fakih

Lenz

Azkarate-Askasua

et al. 2017

Microprocessors and Microsystems

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With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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The ACROSS MPSoC – A new generation of multi-core processors designed for safety–critical embedded systems

Cited by 24 publications

References 8 publications

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Interfaces in Evolving Cyber-Physical Systems-of-Systems

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

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