SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Abstract

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

“…This section summarises power management techniques (based on [2]) that can be used to provide a hypervisor, in particular XtratuM, with low-power features. The techniques are presented independently from a specific hardware platform (the applicable LPT on the Xilinx Zynq platform will be introduced in Section VI).…”

“…The integration of real-time applications is becoming fundamental in the development of complex embedded systems. In some domains, this integration is often required to satisfy nonfunctional requirements related to cost, weight or power consumption [1], [2]. Multicore processors using hypervisors as software execution environments are one possible solution for many systems which require significant computational power from the underlying platform [3].…”

“…Notice that this work has been founded by the European project SAFE-POWER, that aims at the development of a concept hardware-software architecture that relies on both the ARM cores and the PL[21],[2] …”

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

“…The SAFEPOWER (http://www.safepower-project.eu) project aims at providing a reference architecture, which demonstrates the applicability of low-power techniques for mixed-criticality systems [10]. In our previous publications [2,[10][11][12][13], we have addressed the fulfilment of several indispensable requirements by our suggested SAFEPOWER architecture to enable the usage of low-power management techniques in mixed-criticality systems. Table 1 depicts our prior contributions and positions our current work with respect to them.…”

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

“…CON-TREX [3] or SafePower [4], analyze the execution of parallel applications with different criticality levels on such devices, having the goal of reducing their overall power consumption. Since these systems are often battery-driven and/or have constraints regarding size, weight and temperature, the configuration of their power management features plays a major role in system design, to save energy and to reduce system's temperature.…”