A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

Poggi, Tomaso; Onaindia, Peio; Azkarate-askatsua, Mikel; Grüttner, Kim; Fakih, Maher; Peiró, Salvador; Balbastre, Patricia

doi:10.1109/dsd.2018.00054

Cited by 11 publications

(2 citation statements)

References 17 publications

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“…Onaindia et al propose an architecture oriented to realtime systems that monitors and it is able to reduce system power consumption [86]. The lowest-level component of this architecture is a hypervisor.…”

Section: Xtratummentioning

confidence: 99%

A Comprehensive Survey on the Use of Hypervisors in Safety-Critical Systems

2023

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Virtualization has become one of the main tools for making efficient use of the resources offered by multicore embedded platforms. In recent years, even sectors such as space, aviation, and automotive, traditionally wary of adopting this type of technology due to the impact it could have on the safety of their systems, have been forced to introduce it into their day-to-day work, as their applications are becoming increasingly complex and demanding. This article provides a comprehensive review of the research work that uses or considers the use of a hypervisor as the basis for building a virtualized safetycritical embedded system. Once the hypervisors developed or adapted for this type of system have been identified, an exhaustive qualitative comparison is made between them. an exhaustive qualitative comparison is made between them. To the best of our knowledge, this is the first time that all this information is collected in a single article. Therefore, the main contribution of this article is that it collects and categorizes the information of each hypervisor and compares them with each other, so that this article can be used as a starting point for future researchers in this area, who will be able to quickly check which hypervisor is best suited to their research needs.

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Section: Xtratummentioning

confidence: 99%

A Comprehensive Survey on the Use of Hypervisors in Safety-Critical Systems

2023

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“…In the software applications [10,11], the memory blocks could not be de-allocated during the execution time, so the data requests are not processed on the same embedded systems. Moreover, the static memory allocation models [12] cannot predict the required amount of memory for the real time applications, which results in an increased memory overhead. Due to these facts, the dynamic memory management techniques [13] are highly preferred for the modern embedded systems, since it efficiently allocates the memory blocks for execution.…”

Section: ░ 1 Introductionmentioning

confidence: 99%

A Classy Memory Management System (CyM2S) using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) Algorithm for the Real Time Embedded Systems

Sundari

Narmadha

Ramani³

2022

IJEER

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Due to an increased scalability, flexibility, and reduced cost complexity, the dynamic memory allocation models are highly preferred for the real-time embedded systems. For this purpose, the different types of dynamic models have been developed in the conventional works, which are highly focused on allocating the memory blocks with increased searching capability. However, it faced some of the problems and issues related to the factors of complex operations, high time consumption, memory overhead, and reduced speed of processing. Thus, this research work objects to design an advanced and intelligent dynamic memory allocation mechanism for the real-time embedded systems. Here, a Classy Memory Management System (CyM2S) is developed by using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) algorithm for efficiently allocating the memory blocks with simple searching. The CyM2S helps to reduce the fragmentation rate and time consumption by optimally allocating the memory blocks. In this model, the small buffer has been maintained for surplus pointers, and the allocated blocks comprise the metadata and payload data. During evaluation, the performance of the proposed CyM2S- ID2LMA technique is validated and compared by using the measures of memory allocation time, release time, execution, and processing speed.

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