TFMS Microstrip line modelling and characterization up to 110 GHz on 45 nm node silicon technology: application for CAD

Enhanced performance of a 60-GHz power amplifier by using slow-wave transmission lines in 40 nm CMOS technology

“…However, the improvement of performance which can be provided by this kind of Tlines is very limited because of its poor quality factor Q (e.g. For comparison issue, microstrip Tlines presenting the state-of-the-art performance are simulated with the model developed in [19]. For comparison issue, microstrip Tlines presenting the state-of-the-art performance are simulated with the model developed in [19].…”

“…To simplify the EM simulation structure and to save the computing time and memory, a method for calculating the equivalent relative permittivity of the multilayer dielectric developed in [21] was applied. Concerning TFMS Tline, the characteristics come from a proposed model [19] based on previous measured TFMS TLines. For S-CPW Tline, measurements are compared to electromagnetic simulations.…”

“…Q < 10 in [12]), especially at high frequency. For comparison issue, microstrip Tlines presenting the state-of-the-art performance are simulated with the model developed in [19]. As shown in Fig.…”

“…For S-CPW Tline, measurements are compared to electromagnetic simulations. Concerning TFMS Tline, the characteristics come from a proposed model [19] based on previous measured TFMS TLines. The geometric dimensions of the S-CPW Tline have been given in the previous section.…”

Characterizing 10 nm node based BEOL interconnects at low-frequency regime based on a transmission-line modelling approach

“…For this reason, many attempts to model and characterize BEOL structures and their resistance and capacitance have been recently proposed, including their trend of variation when the geometry is scaled-down [6][7][8][9][10][11][12][13]. Nevertheless, the corresponding properties when operated under AC stimuli have not been studied in detail for deepsub-100 nm technologies [14][15][16]. Furthermore, bear in mind that in spite of the relatively short lines used for interconnecting devices within practical implementations, considerably longer lines are used for testing purposes to reduce the measurement and parameter determination uncertainty [7].…”