Testing of Stuck-Open Faults in Nanometer Technologies

Champac, Victor; Hernández, Julio; Barceló, Salvador; Gómez, R.; Hawkins, C.F.; Segura, J.

doi:10.1109/mdt.2012.2205609

Cited by 10 publications

(9 citation statements)

References 23 publications

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“…According to the work in [18], some recommendations can be followed when configuring the faulty gate and the corresponding downstream gates to minimize the influence of leakage currents. In the above example, three combinations for inputs (B C) can be used to propagate the fault.…”

Section: Test Recommendationsmentioning

confidence: 99%

“…In fact, new paradigms have arisen which appeal for the revision of the classical model to extend the detectability of these faults in nanometer technologies. In this direction, the works in [17] and [18] demonstrate the influence of leakage on the behavior of the faulty cells affected by the SOFs. Downstream parasitic capacitances related to the faulty node, which were considered a second-order factor in past technologies, also arise as a nonnegligible factor.…”

Section: Introductionmentioning

confidence: 97%

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Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

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Section: Test Recommendationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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“…The results manifested that when the number of faults is large enough, the defect can be captured by SOF or delay fault tests. Champac et al [13] presented the problem of SOF detection for small nanometer technologies. They proposed a new multiple test vector mechanism to enhance the probability of SOF detection.…”

Section: Background and Motivationmentioning

confidence: 99%

“…For instance, stuck-at [11], delay [12], stuck-Open [13], and bridging fault [14] are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts [15], [16], stuck-Open/stuckOn [17], [18], and gate oxide short (GOS) [19].…”

Section: Introductionmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

Gaillardon

Micheli

2015

IEEE Trans. Nanotechnology

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Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

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“…For instance, stuck-at [8], delay [9], stuck-open [10], and bridging fault [11] are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts [12,13], stuck-open/stuck-on [14,15], and Gate Oxide Short (GOS) [16].…”

Section: Introductionmentioning

confidence: 99%

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.

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Testing of Stuck-Open Faults in Nanometer Technologies

Cited by 10 publications

References 23 publications

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

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