Testing of Configurable 8T SRAMs for In-Memory Computing

Li, Jin-Fu; Tsai, Tsai-Ling; Hsu, Chun-Lung; Sun, Chi-Tien

doi:10.1109/ats49688.2020.9301535

Cited by 9 publications

(12 citation statements)

References 22 publications

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“…To satisfy these two requirements, two NAND operations were added to the March C-test algorithm to finally cover the functional faults of the 8T SRAM-based IMC in both operating modes. Modifications have been made to the March C-test algorithm [2] in order to test IMC memory based on configurable 8T SRAM cells in both SRAM and TCAM operating modes. In summary, [2] and [3] proposed March-like test algorithms to test the proper IMC operation of 8T SRAM memories.…”

Section: Incorrect Behavior R<20kωmentioning

confidence: 99%

“…One of the most promising alternatives is to use In-Memory Computing (IMC) architectures [2] [3]. Beyond their classical storage function, these memory architectures aim at integrating extra logic in the memory array and in the periphery to circumvent the von Neumann bottleneck problem.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, testing IMC architectures must be done in two different modes of operation: i) during memory mode where the memory function (storage, read and write operations) must be tested and ii) during computing mode where operations allowed by the architecture must be tested. So, testing IMC memories is much more difficult than testing conventional memories [2]. Consequently, developing test solutions for IMC architectures is mandatory to enable a widespread use of this new computing paradigm in modern data processing units.…”

Section: Introductionmentioning

confidence: 99%

“…To the best of our knowledge, only two solutions for functional testing of IMC memories based on volatile 8T SRAM cells have been reported in the literature [2] [3]. In [2], authors propose a March-like test for an IMC memory with SRAM and TCAM functions. The March-like test can fully cover simple functional faults in SRAM mode and comparison faults in TCAM mode.…”

Section: Introductionmentioning

confidence: 99%

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Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

Ammoura

Flottes

Girard

et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.

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Section: Incorrect Behavior R<20kωmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

Ammoura

Flottes

Girard

et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

View full text Add to dashboard Cite

show abstract

“…Hence, efficient techniques for production testing and for periodic maintenance testing are mandatory to guarantee the required quality standards. However, advances in memory technology and system design have turned memory testing into a nontrivial task [ 2 , 3 , 4 ]. The complexity of the memory chips makes fault modeling and testing an evermore challenging problem.…”

Section: Introductionmentioning

confidence: 99%

Transparent Memory Tests Based on the Double Address Sequences

Mrozek

Yarmolik

2021

Entropy

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An important achievement in the functional diagnostics of memory devices is the development and application of so-called transparent testing methods. This is especially important for modern computer systems, such as embedded systems, systems and networks on chips, on-board computer applications, network servers, and automated control systems that require periodic testing of their components. This article analyzes the effectiveness of existing transparent tests based on the use of the properties of data stored in the memory, such as changing data and their symmetry. As a new approach for constructing transparent tests, we propose to use modified address sequences with duplicate addresses to reduce the time complexity of tests and increase their diagnostic abilities.

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