Testing of 3D IC with minimum power using genetic algorithm

Kaibartta, Tanusree; Das, Debesh K.

doi:10.1109/idt.2015.7396746

Cited by 2 publications

(1 citation statement)

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“…Power droops induce clock stretching which may lead to a good chip incorrectly failing a timing test [18]. Therefore, power-aware test strategies are very much needed for efficient test power management and many researchers have worked on this issue [16][17][18][19][20][21][22][23][24][25][26][27]. In this paper, we address this issue.…”

Section: Introductionmentioning

confidence: 99%

Approach of genetic algorithm for power‐aware testing of 3D IC

Kaibartta

Giri

Rahaman

et al. 2019

IET Computers & Digital Techniques

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The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promising solution where multiple layers are stacked together decreasing the length of interconnect. However, 3D IC invites some new problems including more complexity in test generation. Testing of 3D IC requires test access architecture called Test Access Mechanism (TAM) for the purpose of transport of test stimuli to the cores placed in different layers. During testing due to increasing switching activity, any circuit demands higher power consumption and it becomes more acute for 3D IC. Moreover, testing of 3D ICs has other constraints. In this study, the authors address the issue of 3D IC testing using genetic algorithm-based approach to decrease test time. At first, available TAM width is partitioned into some fixed groups and they have to find partitioning of TAM and distribution of cores among layers with a goal to decrease test time. Next, they do the same considering, variable partitions with or without certain power limits. Experimental results establish the efficacy of the authors' method.

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