Testing MRAM for Write Disturbance Fault

Su, Chao‐Ton; Tsai, Chih-Wea; Wu, Cheng‐Wen; Hung, Chien-chung; Chen, Young-Shying; Kao, Ming-Jer

doi:10.1109/test.2006.297702

Cited by 17 publications

(23 citation statements)

References 16 publications

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“…Fig. 2 shows the measured operating region distribution of a 1-Mb toggle MRAM chip [6], which comes from the intersection of all cells' operating regions. The distribution shows the percentage of cells that are correctly operated under different levels of (I WWL , I WBL ).…”

Section: Mram Device Operating Region Shiftmentioning

confidence: 99%

Write Current Self-Configuration Scheme for MRAM Yield Improvement

Chen

Wang

2013

IEEE Trans. VLSI Syst.

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Magnetic random access memory (MRAM) is an emerging nonvolatile memory, which is widely studied for its high speed, high density, small cell size, and almost unlimited endurance. However, for deep-submicrometer process technologies, significant variation in the MRAM cells' operating condition results in write failures in cells and reduces the production yield. Memory designers have to characterize failed MRAM chips to find a suitable current level for reconfiguring their write current, which is time consuming. In this paper, we propose an efficient operating-current search method and the corresponding built-in circuit for toggle MRAM, which can rapidly find the minimal operating current. With the built-in search circuit, an MRAM chip can dynamically configure its write current through few tester channels. The resulting chip works correctly and consumes lower power. Production yield, thus, can be increased while the test cost is greatly reduced. We also present a generator of the circuit, which determines the circuit parameters according to the memory specifications and user requirements, and automatically generates the corresponding modules.Index Terms-Built-in self-test (BIST), characterization, memory testing, magnetic random access memory (MRAM), yield enhancement.

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Section: Mram Device Operating Region Shiftmentioning

confidence: 99%

Write Current Self-Configuration Scheme for MRAM Yield Improvement

Chen

Wang

2013

IEEE Trans. VLSI Syst.

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“…The new MRAM fault model-write disturbance fault (WDF)-is proposed in [10]. The data storing/switching mechanism of MRAM is based on the resistance change of the magnetic tunnel junction (MTJ) device in each cell.…”

Section: Write Disturbance Fault (Wdf) Modelmentioning

confidence: 99%

“…For example, WDF´ Óµ denotes the WDF of a victim where the number of aggressors with lower address than the victim is even, and those with higher address than the victim is odd. In [10], we show that the March C test algorithm [36] detects WDF, but is not good enough for distinguishing it from other faults, while a March-½ AE test algorithm [37] is shown to be capable of doing that.…”

Section: Write Disturbance Fault (Wdf) Modelmentioning

confidence: 99%

“…Among them, MRAM is considered a good choice thanks to its high speed, low operating voltage, and virtually unlimited Read/Write endurance [2]- [8]. We therefore see a growing need for MRAM testing and diagnosis methodologies [9], [10].…”

Section: Introductionmentioning

confidence: 99%

“…In [9], the authors propose some defect models based on SPICE simulation for asteroid MRAM. Later, the Write Disturbance Fault (WDF) model for toggle MRAM is proposed [10], which is a fault that affects the data stored in the MRAM cells due to excessive magnetic field generated during the Write operation. Built-in self-test (BIST) also can be developed for MRAM, though so far it is widely used for RAM (and for some flash memory) products to reduce test cost (see, e.g., [15]- [26]).…”

Section: Introductionmentioning

confidence: 99%

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Diagnosis for MRAM write disturbance fault

Tsai

et al. 2007

2007 IEEE International Test Conference

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To help improve quality and yield of magnetic random access memory (MRAM), we propose an adaptive diagnosis algorithm (ADA) that can efficiently identify the write disturbance fault (WDF) for MRAM. The proposed test algorithm is a Marchbased one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). However, the proposed test method can evaluate the process stability and uniformity using logical test method. We also develop a BIST circuit that supports the proposed WDF diagnosis test method. We propose the BIST scheme based on the Decision Write mechanism of the toggle MRAM to reduce total test time. A 1Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15 m CMOS technology. The BIST circuit overhead is only about 0.04% with respect to the 1Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the Decision Write mechanism.

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Introduction

Wang

Stroud

Touba

2008

System-on-Chip Test Architectures

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ABOUT THIS CHAPTEROver the past three decades, we have seen the semiconductor manufacturing technology advance from 4 microns to 45 nanometers. This shrinkage of feature size has made a dramatic impact on design and test. Now we find system-on-chip (SOC) and system-in-package (SIP) designs that embed more than 100 million transistors running at operating frequencies in the gigahertz range. Within this decade, there will be designs containing more than a billion transistors. These designs can include all varieties of digital, analog, mixed-signal, memory, optical, microelectromechanical systems (MEMS), field programmable gate array (FPGA), and radiofrequency (RF) circuits. Testing designs of this complexity is a significant challenge, if not a serious problem. Data have shown it is beginning to require more than 20% of the development time to generate production test patterns of sufficient fault coverage to detect manufacturing defects.Additionally, when the SOC design is operated in a system, soft errors induced by alpha-particle radiation can adversely force certain memory cells or storage elements to change their states. These soft errors can cause the system to malfunction. As complementary metal oxide semiconductor (CMOS) scaling continues, the combined manufacturing defects and soft errors start to threaten the practicality of these nanometer SOC designs.In this chapter, we first describe the importance of SOC testing and review the design and test challenges reported in the International Technology Roadmap for Semiconductors (ITRS). Next, we outline the Institute of Electrical and Electronics Engineers (IEEE) standards used for testing SOC designs. These include the 1149.1 and 1149.6 boundary-scan standards, the 1500 core-based test and maintenance standard, and the 1149.4 analog boundary-scan standard. Some SOC design Reliability and System AvailabilityTraditionally, component reliability, also called device reliability, is measured by acceptable defect level (defective PPM), failure rate per 1000 hours, noise characteristics, etc. Because process yield and fault coverage affect defect level, reliability screen methods, such as stress testing (through burn-in) and I DDQ testing (by measuring the device leakage currents), are often used to accelerate the failure rate

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Testing MRAM for Write Disturbance Fault

Cited by 17 publications

References 16 publications

Write Current Self-Configuration Scheme for MRAM Yield Improvement

Write Current Self-Configuration Scheme for MRAM Yield Improvement

Diagnosis for MRAM write disturbance fault

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