Test resource partitioning and optimization for SOC designs

Larsson, Erik; Fujiwara, Hideo

doi:10.1109/vtest.2003.1197669

Cited by 14 publications

(11 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Most prior work on wrapper/TAM optimization for SoCs has assumed a nonhierarchical test infrastructure [11], [12], [13], [14], [15], [16], [17], [18], [19], [21], [22], [23], [24], [25], [26], [27]. In comparison, only a limited amount of work has been done on wrapper design and TAM optimization for SoCs with hierarchical cores.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Various wrapper design [7], [9], [10] and test access infrastructure optimization algorithms [11], [12], [13], [14], [15], [16], [17], [18], [19] have been described in the literature. Unfortunately, all these methods unrealistically assume that there is no hierarchy inside the embedded cores.…”

Section: Introductionmentioning

confidence: 99%

“…Wrappers, TAMs, and test schedules created as if the SoC was nonhierarchical are typically not valid for SoCs with hierarchical cores. Therefore, test solutions proposed by the methods in [7], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], and [19] are not directly applicable to real-life SoCs. There is a need for wrapper design and TAM optimization techniques that can handle hierarchical SoCs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Goel

Marinissen

Sehgal

et al. 2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "child" cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling is hierarchy oblivious, i.e., these techniques treat all cores in an SoC as if they are at the same level of hierarchy. We first show that the test architecture, consisting of wrappers and TAMs, and the corresponding test schedule designed for nonhierarchical SoCs are not valid for SoCs with hierarchical cores. Next, we present two approaches for efficient testing of SoCs with hierarchical cores. In the first approach, the problem is solved by extending a conventional wrapper design; this approach leaves full flexibility for TAM optimization and test scheduling. The second approach is based on a modified wrapper design for parent cores that operates in two disjoint modes for testing of parent and child cores. This approach has an impact on the test architecture and corresponding schedule. We show how an existing test architecture design algorithm can be adapted for use with both approaches. Experiments with the ITC'02 SoC Test Benchmarks show that the first approach offers lower test application times, while the second approach incurs less area costs.

show abstract

Section: Related Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Goel

Marinissen

Sehgal

et al. 2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…SI-related problems are aggravated in core-based SOC designs because interconnects carrying signals between embedded cores tend to be long and hence they suffer more from parasitic effects [Nordholz et al 1998]. Despite this problem, most prior work in SOC test-architecture optimization has focused on core-internal test (InTest) only [Ebadi and Ivanov 2003;Goel and Marinissen 2002;Iyengar et al 2002;Larsson and Peng 2002;Larsson and Fujiwara 2003;Nahvi and Ivanov 2004;Xu and Nicolici 2004;Zhao and Upadhyaya 2005;Zou et al 2003] and neglected the problem posed by core-external interconnect SI faults. The test time for SI faults is long because of the need to exercise a large number of signal-state combinations for the interconnects [Sirisaengtaksin and Gupta 2002; et al.…”

Section: Introductionmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

show abstract

“…Since the gate count of these blocks can be large, the question is how can they be tested effectively? One approach is to treat them as interconnect circuitry in between wrapped cores and test them as nonscanned sequential logic, as discussed in [23] and [25]. If there is a large number of flip-flops and/or latches in the unwrapped logic blocks, this approach may present several problems.…”

Section: Introductionmentioning

confidence: 99%

Modular and rapid testing of SOCs with unwrapped logic blocks

Nicolici

2005

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.

show abstract

Test resource partitioning and optimization for SOC designs

Cited by 14 publications

References 18 publications

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Modular and rapid testing of SOCs with unwrapped logic blocks

Contact Info

Product

Resources

About