Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

Apostolakis, A.; Gizopoulos, Dimitris; Psarakis, Mihalis; Ravotto, D.; Reorda, Matteo Sonza

doi:10.1109/mdt.2009.43

Cited by 31 publications

(16 citation statements)

References 12 publications

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“…A common approach to test communication peripherals adopts the loop-back configuration [5]: during the test, two channels are selected and directly connected. One reads the data sent by the other, and by checking whether the received data correspond to the sent one, a reasonable test of the peripheral can be performed.…”

Section: B Miniuart Case Of Studymentioning

confidence: 99%

Increasing fault coverage during functional test in the operational phase

Carvalho

Bernardi

Sanchez

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly describe fault coverage figures to be achieved. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation exists between the system company and the device provider. However, purely functional test often shows several limitations due to the limited accessibility that it can gain on some input/output signals. This paper proposes a hybrid approach, in which a suitable hardware module is added outside a microcontroller to increase its functional testability during the operational phase. Experimental results gathered on a couple of cases-of-study are reported, showing the feasibility of the method.

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Section: B Miniuart Case Of Studymentioning

confidence: 99%

Increasing fault coverage during functional test in the operational phase

Carvalho

Bernardi

Sanchez

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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“…In that approach, the test sets for the individual subcomponents of the communication peripheral core are precomputed and pre-generated. In [6] the authors propose a combination of the approaches presented in [12] and [13] and define a new automatic methodology. The proposed methodology has been evaluated on a sample SoC with three popular communication peripherals (a UART, an HDLC and an Ethernet controller).…”

Section: A Backgroundmentioning

confidence: 99%

“…The work outlined in [6] focuses on the test of communication peripherals (e.g., serial and output ports); the proposed solution is mainly based on two phases: in the first, the peripheral is suitably configured; in the second, it is correspondingly activated, and its behavior observed. If the peripheral is intended to support the communication between the SoC and the outside world, the latter phase requires the coordinated excitation and/or observation of the peripheral external ports, while the SoC reads/writes the data received/transmitted by the peripheral.…”

Section: Introductionmentioning

confidence: 99%

A software-based self-test methodology for system peripherals

Grosso

Perez

Ravotto

et al. 2010

2010 15th IEEE European Test Symposium

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Software-based self-test strategies have been mainly proposed to tackle microprocessor testing issues, but may also be applied to peripheral testing. However, testing highly embedded peripherals (e.g., DMA or Interrupt controllers) is a challenging task, since their observability and controllability are even more reduced compared to microprocessors and to peripherals devoted to I/O communication (e.g., serial or parallel ports). In this paper we describe an approach to develop functional tests for system peripherals embedded in SoCs that can be used for both design validation and testing. The presented methodology requires two correlated phases: module configuration and module operation. The first one prepares the peripheral on the different operation modes, whereas, the second one is in charge of exciting the whole device and observing its behavior. A methodology for generating suitable test programs is proposed, and preliminary experimental results demonstrating the method effectiveness for an embedded DMA controller are finally reported.

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“…Starting from the first attempt to develop functional tests for microprocessors proposed by Thatte et al in 1980 [4], a rich literature has been produced. Publications propose methods for effectively writing programs for the test of whole microprocessors [5], special modules (e.g., branch prediction units [6], or cache memories [7]), and peripherals components [8].…”

Section: Introductionmentioning

confidence: 99%

On the on-line functional test of the Reorder Buffer memory in superscalar processors

Carlo

Sánchez

Reorda

2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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The Reorder Buffer (ROB) is a key component in superscalar processors. It enables both in-order commitment of instructions and precise exception management even in those architectures that support out-of-order execution. The ROB architecture typically includes a memory array whose size may reach several thousands of bits. Testing this array may be important to guarantee the correct behavior of the processor. Proprietary BIST solutions typically adopted by manufacturers for end-of-production test are not always suitable for on-line test. In fact, they require the usage of test infrastructures that may be expensive, or may not be accessible and/or documented. This paper proposes an alternative solution, based on a functional approach, which has been validated resorting to both an architectural and a memory fault simulator.

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Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

Cited by 31 publications

References 12 publications

Increasing fault coverage during functional test in the operational phase

Increasing fault coverage during functional test in the operational phase

A software-based self-test methodology for system peripherals

On the on-line functional test of the Reorder Buffer memory in superscalar processors

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