A software-based self-test methodology for system peripherals

Grosso, M.; Perez, W. J. H.; Ravotto, D.; Sánchez, Ernesto; Reorda, M. Sonza; Velasco-Medina, Jaime

doi:10.1109/etsym.2010.5512758

Cited by 5 publications

(4 citation statements)

References 15 publications

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“…In [1], the authors present a comprehensive overview of SBST techniques for end-of-manufacturing testing. Similar works proposed solutions for other device subsystems, such as cache memories [10], [11], on-chip memories [12], peripherals [13], and communication components [14].…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

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Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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“…The methodology is suitable for embedded peripherals as well as for stand-alone ones, and improves the deterministic methods presented in [11,12] by providing additional guidelines for achieving high-coverage functional test stimuli starting from highlevel descriptions of the addressed module. Beyond the analysis and stimulation of the operating modes of the selected peripheral, the paper gives details about how to thoroughly excite and observe faults in the most widespread sub-modules that can be found in such devices, by generating a compact set of functional stimuli.…”

Section: Introductionmentioning

confidence: 97%

“…The approach initially presented in [11] aims at system peripherals verification, and it has then been extended to testing [12]. These works propose a method to develop functional tests for DMA controllers embedded in SoCs.…”

Section: Introductionmentioning

confidence: 99%

Software-Based Testing for System Peripherals

Grosso¹,

Holguín²,

Sanchez³

et al. 2012

J Electron Test

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Software-based self-testing strategies have been mainly proposed to tackle microprocessor testing, but may also be applied to peripheral testing. However, testing system peripherals (e.g., DMA controllers, interrupt controllers, and internal counters) is a challenging task, since their observability and controllability are even more reduced when compared to microprocessors and to peripherals devoted to I/O communication (e.g., serial or parallel ports). In this paper an approach to develop functional tests for system peripherals is proposed. The presented methodology requires two correlated phases: module configuration and module operation. The first one prepares the peripheral to work in the different operation modes, whereas the second one is in charge of exciting the whole device and observing its behavior. We propose a methodology that guides the test engineer in building a compact set of test programs able to reach high structural fault coverage levels in a short time. Experimental results demonstrating the method effectiveness for two real-world case studies are finally reported.

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“…Two newer approaches were presented in [11] and [12] by Grosso et al aimed to system peripherals verification and test. These works propose a method to develop functional tests for DMA controllers, and form the basis for the approach presented herein.…”

Section: Introductionmentioning

confidence: 99%

Functional Verification of DMA Controllers

et al. 2011

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Today's SoCs are composed of a wide variety of modules, such as microprocessor cores, memories, peripherals, and customized blocks directly related to the targeted application. To effectively perform simulation-based design verification of peripheral cores, it is necessary to stimulate the description in a broad range of behavior possibilities, checking the produced results. Different strategies for generating suitable stimuli have been proposed by the research community to functionally verify these modules and their interconnection when embedded in a SoC: however, their verification often remains a largely manual and unstructured operation. In this paper we describe a general approach to develop concise and effective sets of inputs by modeling the configuration modes of a peripheral with a graph, and creating paths able to cover all of its nodes: proper stimuli for the device are then directly derived from the paths. The resulting inputs sequences are aimed at design verification of system peripherals such as DMA controllers, and can be applied via simulation by means of dedicated testbenches or by setting up an environment including a processor, which executes a proper test priogram. In the latter case, the developed programs can be exploited in later stages for testing, by adding suitable observability features. Experimental results demonstrating the method effectiveness are reported.

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A software-based self-test methodology for system peripherals

Cited by 5 publications

References 15 publications

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

Software-Based Testing for System Peripherals

Functional Verification of DMA Controllers

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