Functional Verification of DMA Controllers

Grosso, M.; Holguín, Wilson Javier Pérez; Ravotto, D.; Sánchez, Ernesto; Reorda, M. Sonza; Tonda, Alberto; Velasco-Medina, Jaime

doi:10.1007/s10836-011-5219-6

Cited by 2 publications

(1 citation statement)

References 12 publications

(29 reference statements)

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“…Braun et al , (2003) demonstrate that even Bayesian networks and data mining approaches may be used to improve direct random simulation with an autonomous feedback loop, yielding intriguing results. Grosso et al , (2011) study describe a feature packed approach to the production of stimulus for DMA controller design verification. A validation engineer can construct an effective and compact verification set capable of saturating verification metrics in a short time using the suggested approach, relying simply on a high-level description of the DUT.…”

Section: Related Workmentioning

confidence: 99%

A novel utilization-aware and power-delay-aware intelligent DMA controller for video streaming used in AI applications

B.¹,

E.²

2022

IJPCC

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Purpose In real-time entertainment processing applications, processing of the multiple data streams demands high efficient multiple transfers, which leads to the computational overhead for system-on-chip (SoC), which runs the artificial intelligence algorithms. High-performance direct memory access controller (DMAC) is incorporated in SoC to perform the multiple data transfers without the participation of main processors. But achieving the area-efficient and power-aware DMAC suitable for streaming the multiple data remains to be a daunting challenge among the researchers. Design/methodology/approach The purpose of this paper to provide the DMA operations without intervention of central processing unit (CPU) for bulk video data transmissions. Findings The proposed DMAC has been developed based on the hybrid advanced extensible interface (AXI)-PCI bus subsystem to handle the multiple data streams from the video sources. The proposed model consists of bus selector module, user control signal, status register, DMA-supported address and AXI-PCI subsystems to achieve better performance in analysing the video frames. Originality/value The extensive experimentation is carried out with Xilinx Zynq SoC architecture using Very High Speed integrated circuit hardware description language (VHDL) programming, and performance metrics such as utilization area and power are calculated and compared with the other existing DMA controllers such as Scatter-DMA, Gather-DMA and Enhanced DMA. Simulation results demonstrate that the proposed DMAC has outperformed other existing DMAC in terms of less area, less delay and power, which makes the proposed model suitable for streaming multiple video streams.

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Section: Related Workmentioning

confidence: 99%

A novel utilization-aware and power-delay-aware intelligent DMA controller for video streaming used in AI applications

B.¹,

E.²

2022

IJPCC

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An approach to Direct Memory Access module verification

Kutsevol¹,

Meshkov²,

Ryzhov³

et al. 2015

Proceedings of ISP RAS

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A method of direct memory access subsystem verification used for "Elbrus" series microprocessors has been described. A peripheral controller imitator has been developed in order to provide a flexible way to simulate a wide range of workloads of the direct memory access system without a need for computational overhead caused by simulation of the initialization and operation of the southbridge and its controllers. The imitator has been implemented as synthesizable Verilog module used in verification both with the RTL model and with the FPGA prototype. It can be integrated as a replacement of the I/O link connecting the integrated northbridge with the southbridge thus eliminating the need to simulate extra hardware. This connection method allowed to use a single implementation of the imitator with a complete series of microprocessors compatible with respect to the I/O link interface. The model of the imitator was also included into the functional machine simulator. A pseudorandom test generator for verification of the direct memory access subsystem based on the simulator. The test generator has been developed using library version of the functional machine simulator that allowed to use the simulator as a reference model during the test generation. The consistency of the programming interface of the imitator provides ability to execute generated tests unmodified on the functional machine simulator, the RTL model, the FPGA prototype and even the fabricated microprocessors when integrated in the FPGA I/O link controller. Employment of this method allowed to find a significant number of bugs in "Elbrus" series microprocessors being developed.

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Functional Verification of DMA Controllers

Cited by 2 publications

References 12 publications

A novel utilization-aware and power-delay-aware intelligent DMA controller for video streaming used in AI applications

A novel utilization-aware and power-delay-aware intelligent DMA controller for video streaming used in AI applications

An approach to Direct Memory Access module verification

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