Test generation at the algorithm-level for gate-level fault coverage

Bareiša, Eduardas; Jusas, Vacius; Motiejūnas, Kęstutis; Šeinauskas, Rimantas

doi:10.1016/j.microrel.2008.03.017

Cited by 5 publications

(2 citation statements)

References 14 publications

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“…This extra 7 vector reduction can lead to a larger reduction in test cost. To measure the effectiveness of our approach, we compare our results to existing results from [19], [20] and [21]. All circuits were tested with 32 instantiations on the FPGA with a system clock frequency of 25MHz.…”

Section: B Comparison With Commercial Tool and Prior Workmentioning

confidence: 99%

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Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults

Dunbar¹,

Nepal²

2011

JCP

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Abstract-This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. Unlike traditional fault simulation approaches, our approach emulates single stuckat fault behavior in a circuit and finds the minimum test pattern set to detect it. In this paper, we present a method to insert faults into a circuit netlist by identifying circuit fault sites. We then present our parallel method of fault emulation and describe our method to organize and compress the input patterns needed to identify all faults. Using circuits from the ISCAS and MCNC benchmark suites, we show that our approach does better than a commercial tool in test-set reduction.

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Section: B Comparison With Commercial Tool and Prior Workmentioning

confidence: 99%

“…Figure 1 compares and summarizes the results for the different benchmark circuits. Comparisions are made only for the ISCAS circuits as the published work of [19]- [21] do not include results for the MCNC circuits.…”

Section: B Comparison With Commercial Tool and Prior Workmentioning

confidence: 99%