Test Data Volume Comparison: Monolithic vs. Modular SoC Testing

Sinanoglu, Ozgur; Marinissen, Erik Jan; Sehgal, Anuja; Fitzgerald, Jeff; Rearick, Jeff

doi:10.1109/mdt.2009.65

Cited by 18 publications

(6 citation statements)

References 15 publications

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“…The wrapper cells provide scan test access and hence controllability and observability. Wrapper technology enables modular testing [11], in which large stack designs are divided into smaller units, such that ATPG is performed on tractable units, the responsability for test coverage is assigned to whom it belongs (the die maker), test data volume is reduced [25], and reuse in subsequent stack designs becomes easier. Dies can be tested internally while the wrapper is in its inward-facing mode (INTEST) and provides isolation from die-external switching.…”

Section: Overview Of Ieee Std P1838mentioning

confidence: 99%

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Liu

Shao

Jiao

et al. 2018

2018 IEEE 23rd European Test Symposium (ETS)

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IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist. * Yu Li is currently with the ; Ming Shao is currently with Punch Powertrain, ming.shao@punchpowertrain.com; Hailong Jiao is currently also with the Shenzhen Graduate School of Peking University, jiaohl@pkusz.edu.cn. 2018 23rd IEEE European Test Symposium (ETS) !

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Section: Overview Of Ieee Std P1838mentioning

confidence: 99%

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Liu

Shao

Jiao

et al. 2018

2018 IEEE 23rd European Test Symposium (ETS)

Self Cite

View full text Add to dashboard Cite

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“…Additional benefits of a modular test approach are the dedicated focused test pattern generation, possibly with design IP protection [23], lower overall test data volume and application time [25], and first-order diagnosis capability [11].…”

Section: D Test Flowsmentioning

confidence: 99%

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D-and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D-and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.

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“…For an example industrial SOC, typical parameters are n = 8, t = 5000 and s = 10000 [19]. In this example, the parameters yield a total test length T = 50, 025, 008.…”

Section: Scan Chain Test Patternmentioning

confidence: 99%

On Scan Chain Diagnosis for Intermittent Faults

Adolfsson

Siew

Marinissen

et al. 2009

2009 Asian Test Symposium

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Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

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Test Data Volume Comparison: Monolithic vs. Modular SoC Testing

Cited by 18 publications

References 15 publications

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

On Scan Chain Diagnosis for Intermittent Faults

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