On Scan Chain Diagnosis for Intermittent Faults

Adolfsson, Dan; Siew, Joanna; Marinissen, Erik Jan; Larsson, Erik

doi:10.1109/ats.2009.74

Cited by 8 publications

(3 citation statements)

References 21 publications

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“…This is because the primary forces behind a timing violation are the degree of wearout of the circuit combined with the localized temporal variation (temperature and voltage conditions). Such localized temporal variation implies repeated timing violations in a specific pipeline stage/component for several cycles [1]. In such a case, cycle t is unable to borrow time from its own stage in the next clock cycle (t + 1), making it impossible for time borrowing techniques to rectify the timing violation.…”

Section: Back-to-back Dependent Instructions (Bdi)mentioning

confidence: 99%

Predicting timing violations through instruction-level path sensitization analysis

Roy

Chakraborty

2012

Proceedings of the 49th Annual Design Automation Conference

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In this paper, we present a novel technique for early prediction of timing violations in high-performance pipelined microprocessors. We show that a static instruction in a microprocessor, identified by its Program Counter (PC), is an excellent predictor of an upcoming timing violation. Our analysis combines architectural data collected from real program execution with gate level logic analysis. Exploiting this PC based timing violation predictability, we propose a robust system design that predicts and tolerates timing violations seamlessly in a pipelined microprocessor. Under two different faulty environments, we show 20.9-89.8% and 14.6-80.6% average performance improvements in real programs over other state-of-the-art techniques, respectively.

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Section: Back-to-back Dependent Instructions (Bdi)mentioning

confidence: 99%

Predicting timing violations through instruction-level path sensitization analysis

Roy

Chakraborty

2012

Proceedings of the 49th Annual Design Automation Conference

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“…1687 network is without any faults. Several works have addressed testing and localization (diagnostic) for regular scan chains [10]- [12] and for IEEE Std. 1687 networks [13].…”

Section: Related Workmentioning

confidence: 99%

Graceful Degradation of Reconfigurable Scan Networks

Larsson

Xiang

Murali

2021

IEEE Trans. VLSI Syst.

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Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to the fault status of a particular IC. We show how this block enables test for faulty scan chains, localization of faulty scan chains, and repair by excluding faulty scan chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.

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“…The principle to test for faults in scan-chains is built on traditional scan-chain test where a test sequence is shifted through the scan-chain but no capture and update is used [12] [10]. The test scheme includes a test block and a command to perform test of scan-chains.…”

Section: Test Localization and Repairmentioning

confidence: 99%

IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks

Larsson

Xiang

Murali

2020

2020 IEEE European Test Symposium (ETS)

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We address access control of reconfigurable scan networks, like IEEE Std. 1687 networks. We propose an onchip test block to perform: (1) test for faulty scan-chains, (2) localization of faulty scan-chains and (3) repair by excluding faulty scan-chains, and an access control block to (1) control so scanchains (instruments) are only accessed in allowed combinations, (2) detection of access attempts to instrument in not allowed combinations, and (3) monitoring how theses attempts are made. The key features are twofold. First, in respect to operation and maintenance. If the physical implementation of an IEEE Std. 1687 network changes due to faults, the instrument connectivity language (ICL) and procedural description language (PDL) need to be updated. To avoid keeping track and updating ICL and PDL for each individual integrated circuit (IC), proposed test block, placed at each IC, makes adjustments of PDL according to the faults of the particular IC. Second, a centralized access control block with key information about the network to detect and handle unauthorized access.

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On Scan Chain Diagnosis for Intermittent Faults

Cited by 8 publications

References 21 publications

Predicting timing violations through instruction-level path sensitization analysis

Predicting timing violations through instruction-level path sensitization analysis

Graceful Degradation of Reconfigurable Scan Networks

IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks

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