Terabit/sec-class board-level optical interconnects through polymer waveguides using 24-channel bidirectional transceiver modules

Doany, F. E.; Schow, Clint L.; Lee, Benjamin G.; Budd, R.; Baks, Christian; Dangel, R.; John, R.; Libsch, F.; Kash, J. A.; Chan, Benson; Lin, How; Carver, Chase; Huang, Jianzhuang; Berry, J.; Bajkowski, D.

doi:10.1109/ectc.2011.5898601

Cited by 29 publications

(12 citation statements)

References 7 publications

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“…However, for realizing a highdensity optical wiring, a smaller core size (35 35 µm) is anticipated in recent years [10]. As the core size decreases, the rays need to be reflected more frequently at the core-cladding interface in the case of SI-core optical waveguides.…”

Section: Core Size Dependencementioning

confidence: 99%

Crossed polymer optical waveguide for optical printed circuit board

Shitanda

Ishigure

2012

2012 4th Electronic System-Integration Technology Conference

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{ } r r r n grad ds d n ds d = ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ AbstractWe propose to apply graded-index (GI) cores into crossed multimode waveguides. We already confirmed the strong optical confinement effect of GI cores, and thus, GI cores enable to decrease the light leakage at the crossed area, compared to the step-index (SI)-core crossed waveguides. In fact, we calculate the light propagation loss in crossed waveguides with SI and GI cores by developing a ray tracing simulation program. It is found that the GI core shows remarkably lower waveguide loss (0.19 dB for 50-perpendicular crosses) than those of SI core (3.7 dB for the same crossings).

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Section: Core Size Dependencementioning

confidence: 99%

Crossed polymer optical waveguide for optical printed circuit board

Shitanda

Ishigure

2012

2012 4th Electronic System-Integration Technology Conference

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“…The Chemical-Mechanical Planarization (CMP) process is used to remove the copper overburden. The major steps for the TSV process are summarized as following [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]:…”

Section: Large Size Silicon Interposermentioning

confidence: 99%

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Xue

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm x 18 mm x 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm x 10 mm x 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing.The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

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“…It is regarded that the data transmission bottlenecks are shifted from rack-to-rack to board-to-board interconnections and even approaching to board level links [1]. Currently, parallel optical fiber modules have already been utilized for rack-to-rack interconnects in some petaflop-scale HPCs.…”

Section: Introductionmentioning

confidence: 99%

Characterization and analysis of graded index optical waveguides for the realization of low-power, high-density, and high-speed optical link

2012

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This paper describes an advanced optical link model composed of multimode waveguide that is used to aid the development of low-power, high-density, and high-speed multi-channel interconnects. The model consists of a VCSEL, a pair of multi-channel rectangular step-index (SI) or graded-index (GI) type optical waveguides, a graded-index multimode fiber (GI MMF), and a photo detector. Here we assume that each waveguide is integrated on a printed circuit board (PCB), and these two PCBs are connected by the GI MMF ribbon (board-to-board interconnection). Then, we focus on the connection of these link components. For optical links with low-power consumption, the link penalty should be minimized. In this paper, the benefits of GI waveguides over SI waveguides are investigated, particularly about the coupling losses. We start the analysis using the fundamental ray optics. The rays emit from a VSCEL with Gaussian angular intensity distribution. Both between the laser source and the waveguide (Tx side), and between the waveguide and the photodiode (Rx side), a 50 μm gap is assumed, which is filled with a uniform medium with similar refractive index to the core center for the purpose of reducing the Fresnel reflection loss. Furthermore, the two waveguides are connected by a GI MMF, which guides the light from the Tx side to the Rx side. The characteristics such as near field pattern (NFP) and connection loss are addressed. The calculated results show the GI waveguides confine the lightwave intensity near the core center more tightly than the SI waveguide, which result in lower coupling loss (0.46 dB for GI waveguide vs. 1.35 dB for the SI counterpart) between the 35 μm core size waveguides and the 35 μm diameter photo diode (PD). This calculation helps us to characterize the high performance optical link with a more reliable model.

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Terabit/sec-class board-level optical interconnects through polymer waveguides using 24-channel bidirectional transceiver modules

Cited by 29 publications

References 7 publications

Crossed polymer optical waveguide for optical printed circuit board

Crossed polymer optical waveguide for optical printed circuit board

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Characterization and analysis of graded index optical waveguides for the realization of low-power, high-density, and high-speed optical link

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