Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Abstract

The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm x 18 mm x 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm x 10 mm x 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing.The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

Thermal-mechanical responses of 3D IC integration with a passive TSV interposer

“…It can be seen that an interposer with TSVs is supporting a high-performance chip on its top side and another chip on its bottom-side. These chips are arranged into a face-to-face situation so as to achieve better electrical performance [21][22][23][24].…”

Comprehensive Analysis on Hardware Trojans in 3D ICs: Characterization and Experimental Impact Assessment

“…Three-dimensional (3D) integration is an emerging technology to ensure further growth in transistor density and performance of future integrated circuits (ICs) [1,2]. It has been demonstrated that 3D techniques can be leveraged to reduce package size and power consumption while significantly improving bandwidth [3][4][5]. Unfortunately, 3D techniques also bring in unique and unexplored security threats to 3D ICs [6].…”

Through-Silicon Hole Interposers for 3-D IC Integration

“…It can be observed that the interposer is supporting these two chips on its top and bottom sides. In this case, the size of the interposer can be smaller (or more chips can be placed on the same size of interposer), and the electrical performance can be better because the chip-to-chip interconnects are face-to-face instead of side-to-side [13]- [22]. In addition, it is truly a 3-D IC integration with a passive interposer, which will be the focus of this paper.…”