Temperature-induced voltage drop rearrangement and its effect on oxide breakdown in metal-oxide-semiconductor capacitor structure

Wang, Tsung-Miau; Hwu, Jenn–Gwo

doi:10.1063/1.1850199

Cited by 8 publications

(5 citation statements)

References 14 publications

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“…In the depletion region, the slopes of both the forward and backward C-V curves of the nc-CdSe embedded sample decrease with the increase of temperature from 20 o C to 120 o C. This is accompanied with the increase of the interface state density (D it ), i.e., 3.15 ×10 11 cm -2 eV -1 at 20 o C, 3.93 ×10 11 cm -2 eV -1 at 70 o C, and 6.91 ×10 11 cm -2 eV -1 at 120 o C, respectively. The degradation of the interface quality with the increase of temperature has been observed previously [21]. Compared with the nc-CdSe embedded sample, the slopes of the C-V curves of the control sample change little with the change of the temperature.…”

Section: Resultssupporting

confidence: 71%

Temperature Effect on Memory Functions of the nc-CdSe Embedded ZrHfO High-k MOS Device

Zhang

Kuo

2014

ECS Trans.

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The temperature effect on the memory characteristics of the MOS capacitor containing the nanocrystalline CdSe embedded ZrHfO high-k gate dielectric has been investigated. At the high temperature, the Coulomb blockade phenomenon is suppressed and the leakage current is increased due to the relative high conductivity of the dielectric film. At the same time, the density of interface states is high and the memory window is small. When the temperature is increased, the hole trapping capacity is enhanced because of the improve the supply of holes from the Si. However, the electron trapping capacity is reduced because of the easy transfer of electrons through the high-k stack. The frequency dispersion phenomenon is enhanced at the high temperature. The temperature has strong influence on the carrier generation, transport, and trapping at the interface and the bulk film.

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Section: Resultssupporting

confidence: 71%

Temperature Effect on Memory Functions of the nc-CdSe Embedded ZrHfO High-k MOS Device

Zhang

Kuo

2014

ECS Trans.

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“…The emission of the thermionic electrons at the high temperature could cause the damage to the interface. 36 Fig. 4d shows an obvious shoulder between V g = −0.8 V and −1.5 V at 125 • C, which is absent from the control sample at the same temperature.…”

Section: Resultsmentioning

confidence: 90%

Temperature Effects on Nanocrystalline Molybdenum Oxide Embedded ZrHfO High-kNonvolatile Memory Functions

Lin¹,

Kuo²

2012

ECS J. Solid State Sci. Technol.

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Nonvolatile memory characteristics of the MOS capacitor with the nanocrystalline MoOx embedded Zr-doped HfO2 high-k gate dielectric on the p-type Si wafer were studied with respect to the temperature. With the increase of temperature, the memory window was enlarged and the Coulomb blockade effect was suppressed. At the same time, the interface quality was deteriorated, the leakage current was increased, and the lifetime was shortened. Also, the near interface traps were observed at the high temperature and the 1 MHz measurement frequency. They were caused by changes of mechanisms of charge transfer and trapping, such as the formation of the hole-rich accumulation layer, the thermal energy of the accumulated holes, and the electric conductivity of the high-k film.

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“…This indicates that the amount of trap present in the oxide is relatively high when compared with oxides annealed at higher temperatures. 41,42 This trap might subsequently contribute to a high leakage current. As the postdeposition annealing temperature increases, a reduction in oxide capacitance is recorded.…”

Section: H8mentioning

confidence: 99%

Effects of Postdeposition Annealing in Argon Ambient on Metallorganic Decomposed CeO[sub 2] Gate Spin Coated on Silicon

Quah

Cheong

Hassan

et al. 2010

J. Electrochem. Soc.

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Cerium oxide (CeO2) solution was prepared by cerium(III) acetylacetonate hydrate, methanol, and acetic acid as the starting materials via the metallorganic decomposition (MOD) method. Postdeposition annealing was performed onto the MOD-derived CeO2 films deposited onto n-type Si substrates at different temperatures (600, 800, and 1000°C ) under the flow of argon gas. A slow cooling rate was then accomplished for samples to cool down to room temperature. Four orientations [(111), (200), (220), and (311)] of CeO2 films were revealed by X-ray diffraction analysis as well as α-Ce2normalO3 and cerium silicate (Ce2Si2normalO7) . Epitaxial-like behavior was shown in the sample annealed at 600°C due to the (200)-oriented CeO2 film, and the dominance of this plane ceased with the increase in annealing temperature. A negative voltage shift was observed in all of the samples, indicating that positive oxide charges were trapped in the oxide as a result of the presence of oxygen vacancies. An interface trap density was extracted from the capacitance–voltage measurement, and it was related to the current density–voltage characteristics of the investigated samples. The lowest density was perceived by the sample annealed at 1000°C due to the increment in the Ce2Si2normalO7 layer, reduction in total interface trap density, and effective oxide charge.

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Temperature-induced voltage drop rearrangement and its effect on oxide breakdown in metal-oxide-semiconductor capacitor structure

Cited by 8 publications

References 14 publications

Temperature Effect on Memory Functions of the nc-CdSe Embedded ZrHfO High-k MOS Device

Temperature Effect on Memory Functions of the nc-CdSe Embedded ZrHfO High-k MOS Device

Temperature Effects on Nanocrystalline Molybdenum Oxide Embedded ZrHfO High-kNonvolatile Memory Functions

Effects of Postdeposition Annealing in Argon Ambient on Metallorganic Decomposed CeO[sub 2] Gate Spin Coated on Silicon

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