Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

“…The percentage change in the maximum value of switching current is also lower in ISE-SON as compared to SON and ISE thereby showing lesser dependence of power dissipation on operating temperature. This is due to the fact that the degradation in sub-threshold performance with operating temperature is lower in ISE-SON [5] as compared to other devices.…”

“…However, on the basis of the fabrication techniques described for SON [10] and ISE [3] MOSFET architectures separately, the possibility of fabricating ISE-SON MOSFET seems possible. In addition, the analytical modeling scheme proposed earlier for ISE-SON architecture [5] also helps in understanding the device physics of the non-classical architecture and laying down design guidelines for the sub-100-nm device ) are the doping concentration in the channel and the substrate region respectively, (b) Transfer characteristics of SON MOSFET in semi logarithmic scale at different drain biases [2].…”

“…Recently, we proposed a new device architecture called Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET that combines the advantages of Silicon On Nothing (SON) [2] and Insulated Shallow Extension (ISE) MOSFET [3] showing superior device performance as compared to other devices for DC as well as the analog applications even at the higher temperatures [4,5]. The advantage of ISE-SON over the conventional ISE and SON is because of the dielectric isolation provided by the dielectric pillars and the buried oxide layer except the uppermost part of the channel at which the inversion layer is formed.…”

“…The insulating layers effectively suppressed the field penetration from drain to source region and thereby showing reduction in Channel Length Modulation (CLM) and Hot Carrier Effect (HCE) [6]. Previously [4,5] we have already demonstrated that, ISE-SON architecture shows enhanced immunity against the HCE as compared to ISE and SON because of suppressed electron temperature at the drain side. The reduction in electron temperature at the drain side is only because of the presence of side pillars.…”

“…The gate and substrate leakage current are also suppressed in case of ISE-SON architecture as compared to other devices [7]. Although, the suitability of the ISE-SON for analog applications has been discussed in detailed [4,5] but suitability for low-voltage digital application is still not discussed. Thus to explore the advantage of the ISE-SON (as shown in Fig.…”