The advancement of semiconductor industries is a driving force for MOSFET scaling. But as the dimensions of the device are reduced, short channel effects degrade the performance of the device [1]. The scaling of channel length reduces the controllability of gate over the channel region by increasing the charge sharing from source/drain. Due to this, the threshold voltage of MOS device becomes smaller. According to international technology roadmap for semiconductor (ITRS) [2], inclusion of new technologies is turning out to be a critical issue for sub-nanometer MOS devices. Researchers are still working with many device structures to find out a device that can be used in high-frequency application with low power consumption.Since past few decades, the double-gate (DG) MOSFET has shown potential in sub-nanometer regime due to its superb resistance to short channel effects (SCEs) [3]. Researchers have been working with various double-gate structures [4][5][6][7][8][9]. Many theoretical-, simulation-and experimental-based studies have been reported in the literature on DMDG MOSFET. Reddy et al. [10] have reported that the DMDG MOSFET can offer a noteworthy reduction in the hot carrier effects (HCEs). Increased drain breakdown voltage, reduced drain conductance, improved transconductance and desired threshold voltage roll off can be achieved with a DMDG MOSFET below 100 nm channel length. Other than above structures, there are more devices such as quadruple gate [11] MOSFET and Triple Metal Gate Recessed