Temperature-aware test scheduling for multiprocessor systems-on-chip

Abstract

Abstract-Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integrated circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. We first study the power impact of scan chain testing for the ISCAS89 benchmarks. We find that the scan-chain test power consumption is 1.6¢ higher for at-speed testing than normal operating power consumption. We conclude that if the testing frequency is less than half of the normal frequency, then the testing power consumption may in fact be lower. However, due to differences in the cooling environments, the peak die temperatures may still be higher. Second, we present an optimal formulation for minimal-duration temperature-constrained test scheduling. Our results improve on the test schedule time of the best existing algorithm by 10.8% on average for a packaged IC thermal environment. We also present an efficient heuristic that generally produces the same results as the optimal algorithm, while requiring little CPU time, even for large problem instances.

Power and thermal constrained test scheduling

“…We generated chip area, power, floorplan and resource conflict graph information for these benchmarks. Simulation results are shown in Figure I with comparison to the method proposed in [2]. It can be seen that the proposed algorithm performs much better for most of the benchmarks.…”

“…It can be seen that the proposed algorithm performs much better for most of the benchmarks. We can also notice that for the benchmark q1271O, there is no solution for traditional heuristic driven test scheduling scheme given in [2], in which a new test can be scheduled only at times immediately after the completion of the previous test. Our proposed algorithm is capable of inserting cooling periods after some tests to cool down the chip and then find a valid test schedule.…”

Thermal-Aware Test Scheduling Using On-chip Temperature Sensors

“…He et al [4] assumed that running an individual long test will exceed the temperature constraint so they proposed a test set partitioning and interleaving technique and employed constraint logic programming (CLP) to generate thermal-aware test schedules. Bild et al [5] developed an optimal Mixed Integer Linear Programming (MILP) formulation for the thermal-aware test scheduling problem. They also proposed a seed-based clustering heuristic with a phased steady-state thermal model to reduce the thermal simulation time.…”

Thermal issues in test: An overview of the significant aspects and industrial practice

“…They are computed a priori as a static or on-the-fly as dynamic schedule [2] by using an estimation of the power consumed by each test. The power consumption estimation is often derived by logic observations (i.e., switching activity) or use more accurate models.…”