Thermal issues in test: An overview of the significant aspects and industrial practice

Alt, Jurgen; Bernardi, P.; Bosio, Alberto; Kerkhoff, Hans G.; Leininger, A.; Molzer, W.; Motta, A.; Pacha, C.; Pagani, Alberto; Rohani, Alireza; Strasser, Rudolf

doi:10.1109/vts.2016.7477278

Cited by 4 publications

(2 citation statements)

References 12 publications

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“…A functional program requires usually around 10 minutes of cyclic execution to reach stable junction temperature. Even very strong functional procedure are not leading to issues related to thermal behaviors, such as the thermal runway effect [10].…”

Section: Optimization Of Stress Proceduresmentioning

confidence: 99%

An Optimized Test During Burn-In for Automotive SoC

et al. 2018

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The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoCs). This paper proposes an optimized Test-During-Burn-In (TDBI) flow that takes advantage of the parallel execution of several types of stress procedures in which many components are carefully interleaved.The proposed methodology permits to significantly reduce the BI time and enables production monitoring by providing detailed test data-logging capabilities helping the debug of potential yield issues largely caused by the ageing of Burn-In tester consumable parts. The paper describes an experimental scenario about TDBI of an automotive SoC manufactured by STMicroelectronics.

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Section: Optimization Of Stress Proceduresmentioning

confidence: 99%

An Optimized Test During Burn-In for Automotive SoC

et al. 2018

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“…In that case, the resistance will significantly change due to thermo-mechanical stress in PCB soldering as well as chip interconnect (voids, cracks). This has stimulated the idea of controlling local temperatures (in a processor) by means of functional testprogram generation [ALT16]. Along this line, programs were developed (and reused) which can determine the local temperature in a chip accurately, based on certain workloads in parts of a processor [ROH16].…”

Section: B Realistic Fault Evoking Instrumentsmentioning

confidence: 99%

BASTION: Board and SoC test instrumentation for ageing and no failure found

Jutman¹,

Lotz²,

Larsson

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

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