Temperature-Aware Compilation for VLIWProcessors

Schäfer, Benjamin Carrión; Lee, Yongho; Kim, Taewhan

doi:10.1109/rtcsa.2007.69

Cited by 13 publications

(9 citation statements)

References 12 publications

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“…To keep the chip-wide temperature within the thermal capacity of the cooling package, system-level Dynamic Thermal Management (DTM) techniques become indispensable for both high-end general purpose processors [6] and low-power embedded cores [7], [8]. These DTM techniques, such as clock gating [9], fetch toggling [10], and dynamic frequency and voltage scaling [6], control worst-case temperature through globally stalling or slowing down the computation of an overheated core, thus imposing significant performance deterioration.…”

Section: Introductionmentioning

confidence: 99%

Processor reliability enhancement through compiler-directed register file peak temperature reduction

Yang

Orailoğlu

2009

2009 IEEE/IFIP International Conference on Dependable Systems &Amp; Networks

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Abstract-Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliability. Temperature hotspots not only accelerate the physical failure mechanisms such as electromigration and dielectric breakdown, but furthermore make the system more vulnerable to timing-related intermittent failures. Traditional thermal management techniques suffer from considerable performance overhead as the entire processor needs to be stalled or slowed down to preclude heat accumulation. Given the significant temporal and spatial variations of the chip-wide temperature, we propose in this paper a technique that directly targets one of the resources that is most likely to overheat in current processors, namely, the register files. Instead of duplicating or physically distributing the register file, we suggest to attain power density control through exploiting the extant spatial slack associated with register file accesses. Based on application-specific access profiles, a compiler-directed register shuffling strategy is proposed to deterministically construct the logical to physical register mapping in a rotating manner. Simulation results confirm that the proposed technique attains, within a limited hardware budget and negligible performance degradation, effective reduction in peak temperature and hence in the expected fault rates for the entire chip.

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Section: Introductionmentioning

confidence: 99%

Processor reliability enhancement through compiler-directed register file peak temperature reduction

Yang

Orailoğlu

2009

2009 IEEE/IFIP International Conference on Dependable Systems &Amp; Networks

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“…Some research has been conducted concerning instruction scheduling (see for ex-ample [225,261,275]) and register allocation (see for example [72,153]), but there exists very little on power and temperature-aware instruction selection. The only techniques I could find are those by Lorenz et al [241,242], Bednarski and Kessler [42], and Schafer et al [301], and of these only the first is of any real interest (the integrated code generation approach by Bednarski and Kessler is mostly concerned with instruction scheduling and register allocation, and the technique by Schafer et al only performs functional-unit rebinding of already-selected instructions).…”

Section: Open Aspectsmentioning

confidence: 99%

Instruction Selection

Blindell

2016

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“…This res the upper 48 bits of th of misprediction is on the case of output wid diction may not be kno ming to optimize the idle time placement. Other work [70] proposes a pseudo instruction scheduling technique for VLIW processors that maps parallel instructions to the coolest functional units, and gives for each instruction a possible list of thermally-inactive functional units for temperature reduction.…”

Section: Arithmetic Unmentioning

confidence: 99%