Processor reliability enhancement through compiler-directed register file peak temperature reduction

Abstract

Abstract-Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliability. Temperature hotspots not only accelerate the physical failure mechanisms such as electromigration and dielectric breakdown, but furthermore make the system more vulnerable to timing-related intermittent failures. Traditional thermal management techniques suffer from considerable performance overhead as the entire processor needs to be stalled or slowed down to preclude heat accumulation. Given the significant temporal and spatial variations of the chip-wide temperature, we propose in this paper a technique that directly targets one of the resources that is most likely to overheat in current processors, namely, the register files. Instead of duplicating or physically distributing the register file, we suggest to attain power density control through exploiting the extant spatial slack associated with register file accesses. Based on application-specific access profiles, a compiler-directed register shuffling strategy is proposed to deterministically construct the logical to physical register mapping in a rotating manner. Simulation results confirm that the proposed technique attains, within a limited hardware budget and negligible performance degradation, effective reduction in peak temperature and hence in the expected fault rates for the entire chip.

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers

“…Heat buildup relates closely with the number of accesses to each register. The simulation results in Zhou et al [2008] and Yang and Orailoglu [2009] have confirmed that uniformly distributing register accesses among different registers can effectively reduce the chip-wide peak temperature during program execution. We use Rcount(R x ) to indicate the total number of accesses to a physical register R x .…”

“…(5) The proposed register allocation technique can achieve a reduction of 3.3-6.8 • C in register peak temperature. The peak chip-wide temperature is also reduced by about 3.4-6.6 • C. As discussed in Yang and Orailoglu [2009], even though the amount of temperature reduction seems to be insignificant at first sight, it actually can effectively reduce the fault rate of the entire chip, that is, because previous studies have shown that the fault rate doubles for every 10 • C increase [Lasance 2003], and a large number of delay violations would occur if the peak temperature exceeds 85 • C [Skadron et al 2003]. It can be seen from the results that for most benchmarks, the proposed algorithms can effectively reduce the peak temperature to below 85 • C.…”

“…Zhou et al [2008] conclude that the higher temperature on registers is mostly due to the highly frequent accesses to some groups of registers and propose a register reassignment method which breaks such groups. Yang and Orailoglu [2009] aim to reduce the peak temperature of registers by an access density control through a register shuffling strategy. Hsieh and Hwang [2009] propose two thermal management techniques for registers: register binding to balance the register temperature considering both spatial and temporal thermal information, and a forwarding method to reduce the access counts of registers.…”

ThermOS: System support for dynamic thermal management of chip multi-processors

“…Unfortunately, the effectiveness of this approach is limited by design by the use of the NOP instruction, which does not allow the processor to transition from the C0 to the C1E state. We are aware of state-of-the-art compiler-directed techniques to decrease the peak temperature of a processor to improve long-term reliability [18]; however, these techniques target the mitigation of long-term effects like the negative bias temperature instability and the aging.…”