Register allocation for embedded systems to simultaneously reduce energy and temperature on registers

Abstract

Energy and thermal issues are two important concerns for embedded system design. Diminished energy dissipation leads to a longer battery life, while reduced temperature hotspots decelerate the physical failure mechanisms. The instruction fetch logic associated with register access has a significant contribution towards the total energy consumption. Meanwhile, the register file has also been previously shown to exhibit the highest temperature compared to the rest of the components in an embedded processor. Therefore, the optimization of energy and the resolution of the thermal issue for register accesses are of great significance. In this article, register allocation techniques are studied to simultaneously reduce energy consumption and heat buildup on register accesses for embedded systems. Contrary to prevailing intuition, we observe that optimizing energy and optimizing temperature on register accesses conflict with each other. We introduce a rotator hardware in the instruction decoder to facilitate a balanced solution for the two conflicting objectives. Algorithms for register allocation and refinement are proposed based on the access patterns and the effects of the rotator. Experimental results show that the proposed algorithms obtain notable improvements of energy and peak temperature for embedded applications. ACM Reference Format:Liu, T., Orailoglu, A., Xue, C. J., and Li, M. 2013. Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.

Decreasing Spill Code to Decrease Energy Consumption

“…Another way of reducing memory accesses is through register allocation. Some approaches of register allocation aiming low energy consumption are presented in [9], [10], [11], [12].…”

Bytewise Register Allocation

“…Traditional graph-coloring register allocators, such as Chaitin's original [7] approach, as well as later graph-coloring approaches [14,19] are elegant when used for architectures with interchangeable, non-aliasing registers. While they can be generalized to handle some architectural irregularities [24,26], they cannot handle the extreme irregularities and aliasing resulting from bytewise register allocation well.…”