Technology mapping for standard-cell generators

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks

“…The first one was presented by Berkelaar (1988), and like the first methods for technology mapping, it partitions the circuit into logic cones, but does not use trees to represent them. Expressions of sums-of-products and product-ofsums are represented as graphs, using a prefixed notation.…”

DAG based library-free technology mapping

“…Boolean methods are able to overcome the structural bias [18] of the circuit being mapped, because they do not depend on the DAG structure, but only on the function being mapped. Another important point is that the associative methods to compute series transistor constraints used in [6,7,8,9,10] are monotonically increasing with the association, meaning the association of two functions will always have more transistors in series. The Boolean method is non monotonic, meaning the association of two functions can reduce the number of transistors in series.…”

“…In the early phase of technology mapping, it was considered that the use of a cell generator [6] would enable the use of larger virtual (built on demand) cell libraries. Unfortunately, the use of such approaches was not widely verified in a commercial level, even if other references suggest that the increased number of cells in a library could lead to significant improvements in the quality of the final design [7][8][9][10].…”

Exact lower bound for the number of switches in series to implement a combinational logic cell

“…The main switch topologies used to design transistor networks for logic cells are Pass Transistor Logic (PTL) [1][2][3][4][5][6][7][8] and Complementary Series/Parallel (CSP) CMOS Logic [9][10][11][12]. PTL topology is composed of a single non-disjoint pull-up/down plane, while CSP topology has two disjoint switch planes: one pull-up plane and one pull-down plane.…”

“…Notice that the circuit in Fig. 1.b does not use Complementary Series/Parallel (CSP) logic [9][10][11][12]. The use of CSP topology would produce a network with a transistor chain longer than the PTL version of Fig.…”