Technology and Modeling of Nonclassical Transistor Devices

Abstract

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

Double Gate MOSFETs: Assessment with Single Gate MOSFETs with Channel Material Configuration, its Structure Orientation and Future Applications

“…in particular area doubles shown in Fig. 2, thus in order to accommodate more and more transistors in the particular area dimensions of MOSFETs are decreased continuously (scaling) with more focus has been spend on finding out the highly efficient chips with higher speed performance and lowering cost of transistors per chip with utilization of non-Si materials which have capabilities like higher carrier mobility, high speed device applications and low power consumption so that it can be future alternative for replacing the current single-gate MOSFETs [3][4][5][6][7][8].…”

Dopingfree Schottky Buried Metal Layer Fully Depleted Planar FET for SCE Suppression at sub-28nm Technology Nodes

“…Sub-22 nm technology nodes suffer heavily with limitations of perfect abrupt doping profiles which in-turn yields in performance that does not comply with international technology roadmap of semiconductors (ITRS) projections [3]. Already several technologies different from conventional CMOS have been implemented at industry level that comply with ITRS standards like FinFETs, multigate FETs, junctionless FETs etc [4].…”

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

“…The dramatic development of field-effect transistors manufacturing technology has enabled the growth of modern integrated circuit technology as well as the manufacture of electronic computers, and despite advances in technology for field-effect transistors [8,9], Bipolar Junction Transistors (BJTs) remained dominant over the technologies of manufacturing transistors during the 1960s and 1970s due to Benefits and better performance compared to field effect transistors [10,11]. And that the technology of manufacturing field-effect transistors requires less manufacturing steps than those required in the manufacture of bipolar junction transistors (BJT),  ISSN: 1693-6930 TELKOMNIKA Telecommun Comput El Control, Vol.…”