Techniques to reduce the soft error rate of a high-performance microprocessor

Abstract

Transient faults due to neutron and alpha particle strikes pose a significant obstacle to increasing processor transistor counts in future technologies. Although fault rates of individual transistors may not rise significantly, incorporating more transistors into a device makes that device more likely to encounter a fault. Hence, maintaining processor error rates at acceptable levels will require increasing design effort.

Vulnerability Analysis of L2 Cache Elements to Single Event Upsets

“…Processor pipelines have been studied in [15,23]. L1 caches have been studied in [2,25] and subsequently in [4].…”

An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures

“…So, this type of errors can be classified in the category of Silent Data Corruptions (SDCs) [31][32][33]. If this type of error cause control flow graph violation (i.e.…”

A survey of memory error correcting techniques for improved reliability

“…This makes soft errors an even more common case. Device scaling, reduction in feature size and voltage levels of the transistor, along with high density transistors have increased the risk of hardware faults due to soft errors (Weaver et al, 2004). Studies by Ziegler et al (1996aZiegler et al ( , 1996b claimed that a typical processor's silicon can have a soft-error rate of 4000 FIT, of which 50% will affect processor logic and 50% on-chip cache (Garg).…”