Techniques for fully integrated intra-/inter-chip optical communication

Favi, Claudio; Charbon, Edoardo

doi:10.1145/1391469.1391558

Cited by 8 publications

(6 citation statements)

References 7 publications

(8 reference statements)

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“…While SPADs are photodetectors with exceptionally high time resolution, they lack speed and require a relatively high detection cycle or dead time. To ensure high throughput nonetheless, we have proposed to use pulse position modulation (PPM) applied to the optical pulses [12]. With this scheme it is necessary to implement high throughput time difference discriminators that can be implemented in a very small surface.…”

Section: Introductionmentioning

confidence: 99%

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Favi

Charbon

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed architecture, implemented in a 65nm FPGA system, consists of a pipelined interpolating time-to-digital converter (TDC). The TDC comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300MHz. A Turbo version of the circuit implements a pipelined interpolating TDC with suppressed dead time to reach a conversion rate of 300MS/s at the expense of a systematic asymmetry that requires fast error correction. The TDCs proposed in this paper can be compensated for process, voltage, and temperature (PVT) variations using a conventional charge pump based feedback or a digital calibration technique. Results demonstrate the suitability of the approach for a variety of applications involving high-precision ultra-fast time discrimination, such as optical lifetime sensing, time-of-flight cameras, high throughput comlinks, RADARs, etc.

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Section: Introductionmentioning

confidence: 99%

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Favi

Charbon

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…AMLEDs have a relatively low efficiency and therefore for fast and low power receivers, they should be integrated with highly sensitive photodetectors such as single-photon avalanche diodes (SPADs) [19]. SPADs are p-n junctions biased above breakdown where an incoming photon can trigger an avalanche.…”

Section: B Pulse Position Modulation and Bit Error Ratementioning

confidence: 99%

“…For data communication applications using SPADs, pulse position modulation (PPM) is a modulation scheme of choice [19]. Fig.…”

Section: B Pulse Position Modulation and Bit Error Ratementioning

confidence: 99%

Data Transmission Capabilities of Silicon Avalanche Mode Light-Emitting Diodes

Agarwal

Annema

Hueting

et al. 2018

IEEE Trans. Electron Devices

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The data transmission capabilities of silicon avalanche mode light-emitting diodes (AMLEDs) were investigated and the results are correlated to the multiplication noise and leakage current. The incoming data were modulated using pulse position modulation and the bit-error-rate (BER) and jitter in the transmitted data were measured. The results indicate an intrinsically low speed in terms of BER and jitter. From various size AMLEDs, temperature variations and optical excitations, it is shown that the speed can be improved by using AMLEDs with a (1) relatively high multiplication noise, (2) relatively high leakage current and (3) higher charge-per-bit. Design recommendations for the high speed AMLEDs are discussed.

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“…This will improve the coupling quantum efficiency, as well as reduces the crosstalk among multiple channels in a multi-channel communication environment. If 5 photons are received at the PD per bit, this is typically sufficient to operate a well-designed Single Photon Avalanche Diode (SPAD) as a PD [19,[23][24][25][26][27][28]. SPADs are p-n junctions biased above V BR so that an incoming photon in the depletion region can generate free carriers thus triggering an avalanche [25][26][27].…”

Section: Optocouplers In Cmos Technologymentioning

confidence: 99%

Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

Agarwal¹,

Dutta²,

Annema³

et al. 2017

Opt. Express

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This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant overlap with the responsivity of silicon photodiodes. This enables monolithic CMOS integration of optocouplers, for e.g. smart power applications requiring high data rate communication with a large galvanic isolation. To ensure a certain minimum number of photons per data pulse (or per bit), light emitting diode drivers must be robust against process, operating conditions and temperature variations of the light emitting diode. Combined with the avalanche mode light emitting diode's steep current-voltage curve at relatively high breakdown voltages, this conventionally results in high power consumption and significant heating. The presented transmitter circuit is intrinsically robust against these issues, thereby enabling low power operation.

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Techniques for fully integrated intra-/inter-chip optical communication

Cited by 8 publications

References 7 publications

A 17ps time-to-digital converter implemented in 65nm FPGA technology

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Data Transmission Capabilities of Silicon Avalanche Mode Light-Emitting Diodes

Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

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