Techniques for fabrication of wafer scale interconnections in multichip packages

Fabrication and performance of microbolometer arrays based on nanostructured vanadium oxide thin films

“…In figure 2, the CMOS chip surface roughness reaches 2 μm, so it should be planarized before the subsequent formation of the flat microstructures. Because the microstructure is built on the CMOS chip, it is critical that the IC fabrication must result in a planar surface for ideal microstructural and optical properties [9,10]. The basic micromachining process for building an efficient microbolometer is illustrated in figure 3.…”

Deposition of High Purity Parylene- F Using Low Pressure Low Temperature Chemical Vapor Deposition

“…Cu is currently being examined as a possible replacement for A1 as a conductor material and some polymers, with dielectric constants (e) below 2.5, are being examined as potential insula-(Received April 17, 1996; accepted May 14, 1997) *Also with Department of Physics, Southern Oregon University, Ashland, OR 97520 *Also with Department of Physics *Also with Department of Chemical Engineering ~Also with Department of Chemistry tors. [1][2][3] For a material to be suitable as an interconnect dielectric, it should have a low dielectric constant and be able to withstand 450~ the highest processing temperature currently used in industry. Polymers such as Parylenes 4 and polyimides are suitable for such applications.…”