TDDB robustness of highly dense 65NM BEOL vertical natural capacitor with competitive area capacitance for RF and mixed-signal applications

Fischer, A.; Lim, Y.C.; Riess, P.; Pompl, T.; Zhang, B.C.; Chua, Eng Chye; Keller, Wolfgang; Tan, Jianguo; Klee, Velveth; Tan, Yi; Souche, D.; Sohn, Dong Kyun; Glasow, A. von

doi:10.1109/relphy.2008.4558873

Cited by 15 publications

(3 citation statements)

References 5 publications

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“…We conclude that it is possible to predict S min from measurements of the components of S, obviating the need for physical measurements to determine N (s) and S min for every sample in an experiment. Here, we have assumed that the distributions of v, w, and x do not contain defect sub-populations, [18] but the analysis is readily extended provided these distributions are known. Alternatively, this method of analysis provides a means to readily detect the presence of defective populations within experimental data.…”

Section: A Characterization Of Minimum Dielectric Thicknessmentioning

confidence: 99%

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-$k$ Dielectrics

Lee

Oates

Chang

2010

IEEE Trans. Device Mater. Relib.

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Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low-k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull β with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.Index Terms-Cu/low-k interconnect reliability, line edge roughness (LER), porosity, time-dependent dielectric breakdown (TDDB).

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Section: A Characterization Of Minimum Dielectric Thicknessmentioning

confidence: 99%

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-$k$ Dielectrics

Lee

Oates

Chang

2010

IEEE Trans. Device Mater. Relib.

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“…A discernable interface layer will likely still exist on top of the ULK portion of the trench top surface because subsequent ULK dielectric deposition must occur on top of the metal cap. Thus, via spacing to adjacent metallization is smaller than that normally at the trench top [17,18,243,244]. (5) Vias tend to form distended regions around the top of the via at the trench/capping layer interface that arise from taper effects and via misalignment [242].…”

Section: Interconnect Layout and Test Structuresmentioning

confidence: 99%

Electrical Breakdown in Advanced Interconnect Dielectrics

Ogawa

Aubel

2012

Advanced Interconnects for ULSI Technology

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“…It has been demonstrated in [12] that the direct application of high voltage pulses is very effective for screening, because of the higher acceleration factor related to voltage activated phenomena. However, this approach has never been attempted before, due to the difficult task to apply the required high voltage pulses to the capacitor bank.…”

Section: ) Traditional Screening Procedures For Inter-metal Dielectrmentioning

confidence: 99%

In situ screening techniques for defective oxides in devices for automotive applications

Malandruccolo¹,

Ciappa²,

Fichtner³

et al. 2011

2011 International Reliability Physics Symposium

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Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents novel built-in circuitries to screen out oxide defects in integrated circuits for the most important building blocks used in automotive applications. The proposed techniques are based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept and advantages of the proposed screening procedure are described in very detail and demonstrated experimentally in conjunction with the integration of test-chips.

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TDDB robustness of highly dense 65NM BEOL vertical natural capacitor with competitive area capacitance for RF and mixed-signal applications

Cited by 15 publications

References 5 publications

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-$k$ Dielectrics

Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-$k$ Dielectrics

Electrical Breakdown in Advanced Interconnect Dielectrics

In situ screening techniques for defective oxides in devices for automotive applications

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