Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low-k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull β with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.Index Terms-Cu/low-k interconnect reliability, line edge roughness (LER), porosity, time-dependent dielectric breakdown (TDDB).

We investigate porous low-k SiCOH under dynamic voltage stress to provide new insights into electrical breakdown. Our results are consistent with the existence of two breakdown mechanisms: the first is independent of trench barrier material and other processing details and is identical for DC, unipolar and high frequency bipolar (AC) stress. This mechanism appears to involve permanent physical damage to the dielectric. The second breakdown mechanism is dependent upon process conditions, and is evident only during low frequency bipolar stress. We discuss our findings in terms of breakdown due to the presence of Cu in the dielectric, charge trapping and bond breakage.

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We show that processes used to fabricate advanced porous dielectrics can exhibit reliability approaching the intrinsic capability of the material. Combining this with simulations of failure distributions as a function of porosity and line edge roughness we demonstrate that failure times due to electrical breakdown rapidly decrease below k=2.3. The rapid failure time decrease is due to the statistical nature of increasing porosity (decreasing k), which leads to a shortening of the percolation path for dielectric breakdown. Continued scaling will require greater understanding of the breakdown impact on circuits as well as materials innovations to improve robustness.