TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors

Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation

“…HCD appears to be poorly dependent on the gate voltage in the range of VGS comprised between 2.0V and 2.6V. This result suggests that the peak of the electric field is localized close to the drain side, where the gate and split-gate voltages have a lower impact [1]. The dependence of the drain stress voltage on the onresistance degradation is reported in Fig.…”

“…However, the relatively large gate area, hence the gate capacitance, may limit the dynamic performance of such devices. To mitigate this issue, a separate secondary gate can be considered for the field-plate region, namely split-gate LDMOS [1][2][3][4]. In high-frequency applications, the split-gate contact can be biased with a constant voltage, allowing to reduce the capacitance seen from the gate terminal.…”