Task placement for heterogeneous reconfigurable architectures

Koester, Markus; Porrmann, Mario; Kalte, Heiko

doi:10.1109/fpt.2005.1568523

Cited by 28 publications

(21 citation statements)

References 7 publications

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“…In [10] authors have presented a run-time system for dynamical ondemand reconfiguration. Several research groups, [2,[11][12][13][14][15][16] have built reconfigurable computing engines to obtain high application performance at low cost by specializing the computing engine to the computation task; some preliminary results can be found in the literature, [13,[17][18][19], but no general framework and no publicly available tools are, at the best of our knowledge, available.…”

Section: Introductionmentioning

confidence: 99%

A design flow tailored for self dynamic reconfigurable architecture

Cancare

Santambrogio

Sciuto

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Dynamic reconfigurable embedded systems are gathering, day after day, an increasing interest from both the scientific and the industrial world. The need of a comprehensive tool which can guide designers through the whole implementation process is becoming stronger. In this paper the authors introduce a new design framework which amends this lack. In particular the paper describes the entire low level design flow onto which the framework is based.

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Section: Introductionmentioning

confidence: 99%

A design flow tailored for self dynamic reconfigurable architecture

Cancare

Santambrogio

Sciuto

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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“…Those feasible positions that overlap with many other feasible positions are likely to be blocked by a previously placed instance of another PR module. Thus a reasonable online placement policy is to always select the free position with the least degree of overlap as discussed in [16]. Besides maintaining a large number of free positions at run-time, it is also possible to optimize the placeability of PR modules at design-time.…”

Section: Design-time Optimization Of Pr Modulesmentioning

confidence: 99%

“…The heterogeneity of the resources significantly limits the placement of the PR modules within the PR region. A suitable placement algorithm to handle the heterogeneity is introduced in [16].…”

Section: Introductionmentioning

confidence: 99%

Design Optimizations for Tiled Partially Reconfigurable Systems

Koester

Luk

Hagemeyer

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.

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“…In [24] the authors have presented a run-time system for dynamical ondemand reconfiguration. Several research groups, [6,[25][26][27][28][29][30][31] have built reconfigurable computing engines to obtain high application performance at low cost by specializing the computing engine to the computation task; some preliminary results can be found in the literature, [7,28,[32][33][34][35][36], but no general framework and no publicly available tools are, at the best of our knowledge, available.…”

Section: Overview On Reconfigurable De-signmentioning

confidence: 99%

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

Santambrogio

Sciuto

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Many emerging products in communication, computing and consumer electronics demand that their functionality remains flexible also after the system has been manufactured and that is why the reconfiguration is starting to be considered into the design flow as a new relevant degree of freedom, in which the designer can have the system autonomously modify its functionalities according to the application's changing needs. Therefore, reconfigurable devices, such as FPGAs, introduce yet another degree of freedom in the design workflow: the designer can have the system autonomously modify the functionality carried out by the IP core according to the application's changing needs while it runs. Research in this field is, indeed, being driven towards a more thorough exploitation of the reconfiguration capabilities of such devices, so as to take advantage of them not only at compile-time, i.e. at the time when the system is first deployed, but also at run-time, which allows the reconfigurable device to be reprogrammed without the rest of the system having to stop running. This paper presents emerging methodologies to design reconfigurable applications, providing, as an example the workflow defined at the Politecnico di Milano.

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Task placement for heterogeneous reconfigurable architectures

Cited by 28 publications

References 7 publications

A design flow tailored for self dynamic reconfigurable architecture

A design flow tailored for self dynamic reconfigurable architecture

Design Optimizations for Tiled Partially Reconfigurable Systems

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

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