Today's Field Programmable Gate Arrays (FPGAs) can be reconfigured partially, which makes it possible to share resources between various functional modules (hardware tasks) over time. This concept is well known in the area of conventional operating systems. However, in order to transfer resource sharing concepts to operating systems on FPGAs, several underlying mechanisms have to be developed. One of these mechanisms is to suspend hardware tasks and restart them at another time and/or another area of the FPGA. Addressing this problem, this paper discusses ways to save and restore the state information of a hardware task. Afterwards, an implementation of a state relocation mechanisms is presented that uses the standard configuration port. In contrast to similar approaches, we significantly reduce the amount of readback data by reading only those configuration frames that contain state information. We finally determine the time overhead for task relocation, which is essential for most multitasking concepts, like defragmentation 1 .

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The increasing logic density of current FPGAs (Field Programmable Gate Arrays) enables the integration of whole systems on one programmable chip. Some of these FPGAs provide the additional feature of partial dynamic reconfiguration, which permits to change parts of the device while other parts keep working. Combining the features of system level density and partial dynamic reconfiguration enables the integration of dynamic systems that can be adopted to changing demands during runtime. A lot of theoretical work in this challenging research area has been done on efficiently placing and scheduling modules on the FPGA area. However, there is a lack of applied approaches that can be realized by existing tools and FPGAs. In this paper we present a new, realizable approach for the dynamic system integration on Xilinx Virtex FPGAs. In contrast to the existing approaches that consider fixed slots for the module placement, our approach enables the fine-grained placement of modules with variable width along a horizontal communication infrastructure 1 .

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